Multidimensional representation of ultrasonic data processed by Reconfigurable Ultrasonic System-on-Chip using OpenCL high-level synthesis

2014 IEEE International Ultrasonics Symposium ◽

10.1109/ultsym.2014.0481 ◽

2014 ◽

Cited By ~ 4

Author(s):

Spenser Gilliland ◽

Clementine Boulet ◽

Thomas Gonnot ◽

Jafar Saniie

Keyword(s):

System On Chip ◽

High Level Synthesis ◽

On Chip ◽

High Level ◽

Multidimensional Representation

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A Framework for High-Level Synthesis of System-on-Chip Designs

2005 IEEE International Conference on Microelectronic Systems Education (MSE'05) ◽

10.1109/mse.2005.8 ◽

2006 ◽

Cited By ~ 29

Author(s):

J.E. Stine ◽

J. Grad ◽

I. Castellanos ◽

J. Blank ◽

V. Dave ◽

...

Keyword(s):

System On Chip ◽

High Level Synthesis ◽

On Chip ◽

High Level

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Evaluation of Stencil Based Algorithm Parallelization over System-on-Chip FPGA Using a High Level Synthesis Tool

Communications in Computer and Information Science - Applied Computer Sciences in Engineering ◽

10.1007/978-3-030-31019-6_5 ◽

2019 ◽

pp. 52-63

Author(s):

Luis Castano-Londono ◽

Cristian Alzate Anzola ◽

David Marquez-Viloria ◽

Guillermo Gallo ◽

Gustavo Osorio

Keyword(s):

System On Chip ◽

High Level Synthesis ◽

Synthesis Tool ◽

On Chip ◽

High Level ◽

Algorithm Parallelization

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System-on-Chip Design Using High-Level Synthesis Tools

Circuits and Systems ◽

10.4236/cs.2012.31001 ◽

2012 ◽

Vol 03 (01) ◽

pp. 1-9 ◽

Cited By ~ 7

Author(s):

Erdal Oruklu ◽

Richard Hanley ◽

Semih Aslan ◽

Christophe Desmouliers ◽

Fernando M. Vallina ◽

...

Keyword(s):

System On Chip ◽

High Level Synthesis ◽

Chip Design ◽

On Chip ◽

High Level

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System on Chip Design with Vivado High-Level Synthesis Tool

2019 11th International Conference on Electrical and Electronics Engineering (ELECO) ◽

10.23919/eleco47770.2019.8990595 ◽

2019 ◽

Author(s):

Bans Bilgili ◽

Ceyhun Yamaneren ◽

Kubilay Vatansever ◽

Umut Coltu ◽

Bema Ors

Keyword(s):

System On Chip ◽

High Level Synthesis ◽

Chip Design ◽

Synthesis Tool ◽

On Chip ◽

High Level

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Study of System-on-Chip devices to implement embedded real-time simulators of modular multi-level converters using high-level synthesis tools

2018 IEEE International Conference on Industrial Technology (ICIT) ◽

10.1109/icit.2018.8352393 ◽

2018 ◽

Cited By ~ 2

Author(s):

D. Tormo ◽

R. Vidal-Albalate ◽

L. Idkhajine ◽

E. Monmasson ◽

R. Blasco-Gimenez

Keyword(s):

Real Time ◽

System On Chip ◽

High Level Synthesis ◽

Multi Level ◽

On Chip ◽

High Level

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High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip

10.1007/978-981-10-1073-6 ◽

2018 ◽

Author(s):

Zheng Wang ◽

Anupam Chattopadhyay

Keyword(s):

System On Chip ◽

High Level Estimation ◽

On Chip ◽

High Level

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High Level System-on-Chip Design using UML and SystemC

Electronics, Robotics and Automotive Mechanics Conference (CERMA 2007) ◽

10.1109/cerma.2007.4367776 ◽

2007 ◽

Cited By ~ 1

Author(s):

Blanca Alicia Correa ◽

Juan Fernando Eusse ◽

Danny Munera ◽

Jose Edinson Aedo ◽

Juan Fernando Velez

Keyword(s):

System On Chip ◽

Level System ◽

Chip Design ◽

On Chip ◽

High Level

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Communication-centric high level synthesis metrics for low vertical channel density 3-dimensional Networks-on-Chip

7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC) ◽

10.1109/recosoc.2012.6322897 ◽

2012 ◽

Cited By ~ 2

Author(s):

Haoyuan Ying ◽

Thomas Hollstein ◽

Klaus Hofmann

Keyword(s):

Vertical Channel ◽

High Level Synthesis ◽

Networks On Chip ◽

3 Dimensional ◽

Channel Density ◽

On Chip ◽

High Level

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High-level modeling and exploration of a powerline communication network based on System-on-Chip

Multi-objective Design Space Exploration of Multiprocessor SoC Architectures ◽

10.1007/978-1-4419-8837-9_7 ◽

2011 ◽

pp. 145-170

Author(s):

Marcos Martinez ◽

David Ferruz ◽

Hector Posadas ◽

Eugenio Villar

Keyword(s):

Communication Network ◽

System On Chip ◽

Powerline Communication ◽

High Level Modeling ◽

On Chip ◽

High Level

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A General Approach to High-Level Energy and Performance Estimation in System-on-Chip Architectures

Journal of Low Power Electronics ◽

10.1166/jolpe.2009.1037 ◽

2009 ◽

Vol 5 (3) ◽

pp. 373-384

Author(s):

Sandro Penolazzi ◽

Ahmed Hemani ◽

Luca Bolognino

Keyword(s):

System On Chip ◽

Performance Estimation ◽

Level Energy ◽

And Performance ◽

On Chip ◽

High Level

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