CODE COMPRESSION FOR THE EMBEDDED ARM/THUMB PROCESSOR

Previous code compression research on embedded systems was based on typical RISC instruction code. THUMB from ARM Ltd is a compacted 16-bits instruction set showing a great code density than its original 32-bits ARM instruction. Our research shows that THUMB code is compressible and a further 10-15% code size reduction on THUMB code can be expected using our proposed new architecture – Code Compressed THUMB Processor. In our proposal, Level 2 cache or additional RAM space is introduced to serve as the temporary storage for decompressed program blocks. A software implementation of the architecture is proposed and we have implemented a software prototype based on ARM922T processor, which runs on the ARMulator.

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Code Size Reduction in Heterogeneous-Connectivity-Based DSPs Using Instruction Set Extensions

IEEE Transactions on Computers ◽

10.1109/tc.2005.157 ◽

2005 ◽

Vol 54 (10) ◽

pp. 1216-1226 ◽

Cited By ~ 5

Author(s):

P. Biswas ◽

N.D. Dutt

Keyword(s):

Size Reduction ◽

Instruction Set ◽

Code Size ◽

Instruction Set Extensions

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Identification and Removal of Program Slice Criteria for Code Size Reduction in Embedded Systems

IFIP – The International Federation for Information Processing - Embedded System Design: Topics, Techniques and Trends ◽

10.1007/978-0-387-72258-0_23 ◽

2007 ◽

pp. 269-278

Author(s):

Mark Panahi ◽

Trevor Harmon ◽

Juan A. Colmenares ◽

Shruti Gorappa ◽

Raymond Klefstad

Keyword(s):

Embedded Systems ◽

Size Reduction ◽

Code Size ◽

Program Slice

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Code Size Reduction in Embedded Systems with Redesigned ISA for RISC Processors

International Journal of Computer Applications ◽

10.5120/10690-5594 ◽

2013 ◽

Vol 64 (12) ◽

pp. 38-45

Author(s):

Govindarajalu B ◽

K. M. Mehata

Keyword(s):

Embedded Systems ◽

Size Reduction ◽

Code Size

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Instruction Set Encoding Optimization for Code Size Reduction

2007 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation ◽

10.1109/icsamos.2007.4285728 ◽

2007 ◽

Cited By ~ 1

Author(s):

Michael Med ◽

Andreas Krall

Keyword(s):

Size Reduction ◽

Instruction Set ◽

Code Size

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PARE: instruction set architecture for efficient code size reduction

Electronics Letters ◽

10.1049/el:19991420 ◽

1999 ◽

Vol 35 (24) ◽

pp. 2098 ◽

Cited By ~ 12

Author(s):

Young-Jun Kwon ◽

Xiarong Ma ◽

Hyuk Jae Lee

Keyword(s):

Size Reduction ◽

Instruction Set ◽

Instruction Set Architecture ◽

Code Size ◽

Efficient Code

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Bitmask-based code compression methods for balancing power consumption and code size for hard real-time embedded systems

Microprocessors and Microsystems ◽

10.1016/j.micpro.2011.12.008 ◽

2012 ◽

Vol 36 (3) ◽

pp. 267-279 ◽

Cited By ~ 3

Author(s):

Po-Yueh Chen ◽

Chao-Chin Wu ◽

Ying-Jie Jiang

Keyword(s):

Embedded Systems ◽

Power Consumption ◽

Real Time ◽

Code Size ◽

Code Compression ◽

Hard Real Time

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Algorithm for optimal allocation of limited resources based on the game iteration method

Informacionno-technologicheskij vestnik ◽

10.21499/2409-1650-2019-2-89-99 ◽

2019 ◽

pp. 89-99

Author(s):

V. Ya. Vilisov

Keyword(s):

Optimal Control ◽

Linear Programming ◽

Embedded Systems ◽

Iterative Method ◽

High Speed ◽

Optimal Allocation ◽

Software Implementation ◽

Limited Resources ◽

Matrix Game ◽

Acceptable Accuracy

The article proposes an algorithm for solving a linear programming problem (LPP) based on the use of its representation in the form of an antagonistic matrix game and the subsequent solution of the game by an iterative method. The algorithm is implemented as a computer program. The rate of convergence of the estimates of the solution to the actual value with the required accuracy has been studied. The software implementation shows a high speed of obtaining the LPP solution with acceptable accuracy in fractions or units of seconds. This allows the use algorithm in embedded systems for optimal control.

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