A Study on Current Ripple Reduction Due to Offset Error in SRF-PLL for Single-phase Grid-connected Inverters

Author(s):  
Seon-Hwan Hwang ◽  
Young-Gi Hwang ◽  
Soon-Kurl Kwon
Author(s):  
Paiboon Kiatsookkanatorn ◽  
Napat Watjanatepin

This paper proposes a novel method to reduce voltage and current ripple for the inverters by using three-level inverters with unipolar pulse width modulation (PWM) (3LFB-2U). A simple technique of switching signal generation by using carrier-based dipolar modulation of three-phase three-level inverters is extended to single-phase inverters that can be done by generating all possible switching patterns of the single-phase three-level inverters. Moreover, the concept of carrier-based dipolar modulation and the construction of reference voltages from desired output voltage and added zero voltage to control unipolar switching is also shown. The research results reveal that the proposed method can reduce the voltage and current ripple. Furthermore, the voltage and current harmonics can reduce by 27.80% and 1.79%, respectively less than two-level inverters without a loss of a simple modulation to generate the switching signals.


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