Inter-Signal Timing Skew Compensation Of Source-Synchronized Parallel Links With Incremental Signaling

This thesis deals with inter-signal timing skew compensation of source-synchronized multi-Gbytes/s parallel links with both voltage-mode and current-mode incremental signaling schemes. To compensate for the inter-signal timing skew of parallel links with voltage-mode incremental signaling, an early/late block that detects the rising and falling edges of the pulses generated by inter-signal timing skews at the far end of the channels, and subsequently allocates the optimal sampling point of the sampler of each data bit to maximize the timing margins. Two cascaded delay-locked loops are employed to place the sampling clock to the optimal sampling position of each data bit. To compensate for the inter-signal timing skew of parallel links with current-mode incremental signaling, each current-mode receiver maps the direction of its channel current representing the logic state of the incoming data to two voltages of different values. The feedback at the front-end of the receiver minimizes the dependence of the input imedance of the receiver on the channel current so that data dependent impedance mismatch is minimized. Inter-signal timing skews are compensated by inserting a delay line in each channel.

Inter-Signal Timing Skew Compensation Of Source-Synchronized Parallel Links With Incremental Signaling

This thesis deals with inter-signal timing skew compensation of source-synchronized multi-Gbytes/s parallel links with both voltage-mode and current-mode incremental signaling schemes. To compensate for the inter-signal timing skew of parallel links with voltage-mode incremental signaling, an early/late block that detects the rising and falling edges of the pulses generated by inter-signal timing skews at the far end of the channels, and subsequently allocates the optimal sampling point of the sampler of each data bit to maximize the timing margins. Two cascaded delay-locked loops are employed to place the sampling clock to the optimal sampling position of each data bit. To compensate for the inter-signal timing skew of parallel links with current-mode incremental signaling, each current-mode receiver maps the direction of its channel current representing the logic state of the incoming data to two voltages of different values. The feedback at the front-end of the receiver minimizes the dependence of the input imedance of the receiver on the channel current so that data dependent impedance mismatch is minimized. Inter-signal timing skews are compensated by inserting a delay line in each channel.

A low-voltage CMOS current-mode incremental signaling scheme for high-speed parallel links

Point-to-point parallel links are widly used in short-distance high-speed data communications. For these links, the design goal is not only to integrate a large number of I/Os in the systems, but also to increase the bit rate per I/O. The cost per I/O has to be kept low as performance improves. Voltage and timing error sources limit the performance of data links and affect its robustnest. These kinds of noise impose greater challenges in parallel data links, such as inter-signal timing skew and inter-signal cross-talk. The use of low-cost schemes, such as single-ended signaling, is effected signaficantly [sic] by the voltage and timging [sic] noise. Fully differential signaling schemes, two physical paths per signal channel, significantly increases the cost of system. Therefore, overcoming the voltage noise, keeping the cost low are two challenges in high-speed parallel links. In this thesis, we propose a new current-mode signaling scheme current-mode incremtnal [sic] signaling for high-speed parallel links. Also, the circuits of the receiver called current-integrating receiver are presented. To assess the effectiveness of the proposed signaling scheme, a 4-bit parallel link consisting of four bipolar current-mode drivers, five 10 cm microstrip lines with a FR4 substrate, and four proposed current-integrating receivers is implemented in UMC 0.13[micro]m, 1.2V CMOS technology and analyzed using SpectreRF from Cadence Design Systems with BSIM3V3 device models. Simulation results demonstrate that the proposed current-mode incremental signaling scheme and the current-integrating receiver are capable of transmitting parallel data at 2.5 Gbyte/s.

A low-voltage CMOS current-mode incremental signaling scheme for high-speed parallel links

Point-to-point parallel links are widly used in short-distance high-speed data communications. For these links, the design goal is not only to integrate a large number of I/Os in the systems, but also to increase the bit rate per I/O. The cost per I/O has to be kept low as performance improves. Voltage and timing error sources limit the performance of data links and affect its robustnest. These kinds of noise impose greater challenges in parallel data links, such as inter-signal timing skew and inter-signal cross-talk. The use of low-cost schemes, such as single-ended signaling, is effected signaficantly [sic] by the voltage and timging [sic] noise. Fully differential signaling schemes, two physical paths per signal channel, significantly increases the cost of system. Therefore, overcoming the voltage noise, keeping the cost low are two challenges in high-speed parallel links. In this thesis, we propose a new current-mode signaling scheme current-mode incremtnal [sic] signaling for high-speed parallel links. Also, the circuits of the receiver called current-integrating receiver are presented. To assess the effectiveness of the proposed signaling scheme, a 4-bit parallel link consisting of four bipolar current-mode drivers, five 10 cm microstrip lines with a FR4 substrate, and four proposed current-integrating receivers is implemented in UMC 0.13[micro]m, 1.2V CMOS technology and analyzed using SpectreRF from Cadence Design Systems with BSIM3V3 device models. Simulation results demonstrate that the proposed current-mode incremental signaling scheme and the current-integrating receiver are capable of transmitting parallel data at 2.5 Gbyte/s.

Design Analysis for a Special Serial - Parallel Manipulator Transferring Billet for Hot Extrusion Forging Process

To reduce the downtime and optimize the use of energy and manpower, a serial - parallel manipulator is designed for transferring heavy billets for a specific hot extrusion forging process. To increase the structural rigidity and restrict the end-effector of the robot moving in direction parallel with the ground surface, parallel links are added in between serial links of the manipulator design. This modification of the structure must be considered in the modeling and analyzing. This paper addresses the kinematic modeling, the kinematic performance analysis and the strength analysis for the robot. With respect to the parallel links, the constraint equation is written and put together with the kinematic model. Based on the model formulated, the inverse kinematic, the transferring time, the reachable workspace, the dexterity, and the manipulability index of the robot are analyzed and discussed to demonstrate its kinematical performance. These results are important to assess the working capability and improve the parametric design for the robot. In addition, for verifying the end-effector design in terms of the strength and displacement, the stress distribution and the static deflection of the end-effector module are computed and analyzed by using the computer-aided finite element method (FEM).

Inverse kinematics of a serial-parallel robot used in hot forging process

In hot extrusion forging process, the use of robot arm for transferring heavy billets can reduce downtime, improve productivity, reduce worker fatigue and optimize the use of~energy and manpower. To increase the stiffness of the robot and force the end-effector move in directions parallel with the ground surface, two parallel links are added to a standard serial manipulator. This modification of the structure could make it a bit of challenge in the system modelling and controlling. This paper addresses the inverse kinematics analysis that is the central issue for developing autonomous control modes of the robot application.