Purpose
The design method of high-resolution capacitor arrays was proposed to improve the precision of successive approximation register (SAR) analog-to-digital converters (ADCs) without calibration and optimize the circuit area.
Design/methodology/approach
According to calculation of equivalent series capacitors and change of voltage at the comparator input node, two three-stage structures of capacitor arrays and a general design flow of the multi-stage capacitor arrays were presented. Non-ideal factors on the capacitor arrays were analyzed, and the applications of the two structures were explained based on the capacitor mismatch.
Findings
A multi-stage capacitor array for 16-bit SAR ADCs was implemented. The simulation result shows that its nonlinear error was less than 0.3LSB with no gain error and the sampling capacitance accounted for 92.42% of the total capacitance. Effects of capacitive parasitic and mismatch on capacitor arrays were confirmed.
Originality/value
The proposed method focused on capacitor arrays design of high-resolution SAR ADCs. It effectively reduced nonlinear errors, improved SNR and optimized the area of SAR ADCs. The design method was suitable for SAR ADCs with different resolutions to improve their precision.
