Cryptographic Secrecy Analysis of Adaptive Steganographic Syndrome-Trellis Codes

Compared with traditional steganography, adaptive steganography based on STC (Syndrome-Trellis Codes) has extremely high antidetection ability and has been a mainstream and hot research direction in the field of information hiding over the past decades. However, it is noted, in specific scenarios, that a small number of methods can extract data from STC-based adaptive steganography, indicating security risks related to such algorithms. In this manuscript, the cryptographic secrecy of this kind of steganography is analyzed, on condition of two common attacks: stego-only attack and known-cover attack, respectively, from three perspectives: steganographic key equivocation, message equivocation, and unicity distance of the steganographic key. Focusing on the special layout characteristics of the parity-check matrix of STC, under the two attack conditions, the theoretical boundaries of the steganographic key equivocation function, the message equivocation function, and the unicity distance of the steganographic key are separately obtained, showing the impact of the three elements: the submatrix size, the randomness of the data, and the cover object on the cryptographic secrecy of the STC-based adaptive steganography, resulting in a theoretical reference to accurately judge the cryptographic secrecy of such steganography and design more secure steganography methods.

DESIGN & IMPLEMENTATION OF POLYPHASE FILTER TO DENOISE OFDM SIGNALS

An amazingly effective digital transit system that carries multiple carriers that meet in conjunction with each other over a period of time is known as the Orthogonal Frequency Division Multiplexing (OFDM) system. Among the traditional symbols, there is a need to include a group of guards. However, in OFDM systems this is not required. Although there is an overlap of side bands from each carrier, no interference is involved within the signals found here as they are orthogonal in relation to each other. This research work is based on a wireless channel to reduce the rate of error using space-time trellis codes. In this research project, the minimum error rate is reduced over wireless channels using space time codes and poly-phase filters. The proposed modular simulation is performed at MATLAB and the results show that the minimum bit error rate decreases in the network.

Performance of channels coding and space-time trellis codes on fading channel for multiple-input multiple-output free-space optical communication systems

The authors have requested that this preprint be withdrawn due to a need to make corrections.

Performance of channels coding and space-time trellis codes on fading channel for multiple-input multiple-output free-space optical communication systems

In this paper, we review and analyze the space-time trellis codes with and without ideal beamforming. Space-time trellis code with ideal beamforming at transmitter termed as weighted space. Smart antenna technology provides a wide variety of options, ranging from single-input multiple-output architectures that collect more energy to improve the signal-to-noise ratio at the receiver, to multiple-input multiple-output (MIMO) architectures that open up multiple data pipes over a link. Atmospheric turbulence can cause significant performance degradation in free-space optical (FSO) communication systems. An efficient solution could be to exploit the temporal diversity to improve the performance of the FSO link.

Space-time trellis codes: Field programmable gate array approach

This paper presents an implementation of Space-time Trellis Codes for 4-state on FPGA. To reach the very high data rates provided in STTC, a lot of expensive high-speed Digital Signal Processors (DSPs) should be employed for the real time applications, while it might not be affordable. This fact has motivated in designing dedicated hardware implementations using Field Programmable Gate Array (FPGA) with low cost and power consumption. The hardware device XC3S400, family Xilinx Spartan-3, and package PQ208 are used in this project, in which the STTC encoder and decoder utilizes maximum 10% and 22% as that of available device capacity respectively. The design has been simulated and synthesized successfully in Xilinx integrated software environment.