In this paper, a novel helix delay line with RPs structures is proposed to investigate the performance of crosstalk reduction. In the past, conventional delay lines consist of equal-length parallel unit lines which are closely packed to minimize the fabricated cost and routing area. All spacing between the adjacent parallel unit lines of delay lines should be smaller. When the operating signal frequency ups to the GHz level, the electromagnetic noise has become a dominant issue coupling from adjacent lines. It is called as a crosstalk source. The crosstalk may affect system-level timing. Besides, it causes error switching of logic gates that will reduce the signal quality. The feature of proposed helix delay line is that the far-end crosstalk (FEXT) is a dominated noise that accumulates at the receiving end. RPs structures are added and aligned at the center of the two parallel adjacent unit lines of the proposed helix delay line, which are used to reduce the difference between inductive and capacitive coupling coefficient ratios, and to reduce FEXT that maintains the signal integrity (SI) quality on receiving end.
