Tone mapping is extensively researched to address the issue of displaying high dynamic range (DR) scenes on low DR displays. Even though several tone-mapping operators (TMOs) exist, not all are designed for hard real time. The operator has to be capable of scaling up the spatial resolution without compromising the frame rate. The implementation of a TMO should also be simple enough to embed in low-cost platforms for imaging systems. A computationally efficient, and well accepted, class of TMOs are global ones based on histograms. This work presents a method to implement TMOs that use histograms. This method is suitable for low-cost field-programmable gate arrays (FPGAs), using simple components such as adders, multipliers, and random access memories, and is particularly suited for a nonlinear CMOS image sensor (CIS) operating continuously in hard real time. The authors develop a fixed-point design, validated in bit-true fashion using Xilinx and Altera tools, from a background algorithm implemented using M ATLAB . Our generic design uses pipelined circuits and operates with low latency. The use of a hardware description language to model our circuits guarantees portability and modularity. Moreover, the complete TMO is generated from design parameters and a design template. The architecture is robust and scales well from kilopixel to megapixel formats. The circuits achieve 30 frames per second, at high definition resolutions, while occupying only a small fraction of the available logic elements in a low-cost FPGA device.
Experimental Validation of a Two-Phase Clock Scheme for Fine-Grained Pipelined Circuits Based on Monostable to Bistable Logic Elements