Euler and RK4 Algorithms Based Implementation of Autonomous Chaotic Generator

Chaotic systems plays a vital role in the field of security, data hiding and steganography. FPGA implementation makes more advantageous compared to analog one. Different chaotic systems like chaos generator and nondeterministic number generator used for security purpose and key generation were successfully realized in FPGA. In this paper, FPGA implementation of Pandey-Baghel-Singh chaotic system (PBSCS) using Euler and RK4 numerical algorithms is presented. Pandey-Baghel-Singh chaotic system were obtained using numerical differential solution and numerically modelled in Verilog with the environment of Xilinx Vivado 2017.3 design suite. The design is verified using experimental setup with the help of interfacing to PC and FPGA family of Artix-7 Nexys 4 DDR and Basys3. Performance of the FPGA based chaotic generator using Euler and RK4 algorithm are analyzed using 1 GB data sets with the maximum operating frequency achieved up to 359.71 MH

A memristor-based chaotic-masking for analog spread-spectrum communication

<span>This paper presents a simple chaotic-masking system. The system uses a chaos generator built around a grounded memristor. The memristor is emulated using the current-feedback operational amplifier (CFOA). At the sending end the signal is masked by adding chaos. At the receiving end the signal is recovered by subtracting the chaos. The performance of proposed system is investigated using sinusoidal and square wave signals.</span>

Low Voltage Low Power Fully Integrated Chaos Generator

A low voltage low power fully integrated chaos generator is presented in this paper. Comparing with the conventional off-the-shelf electronic components-based chaos generators, the designed circuit is fully integrated, and it achieves lower supply voltage, lower power dissipation and smaller chip area. The proposed fully integrated chaos generator is verified with GlobalFoundries 0.18[Formula: see text][Formula: see text]m CMOS 1P6M RF process using Cadence IC Design Tools. The simulation results demonstrate that the fully integrated chaos generator consumes only 17[Formula: see text]mW from [Formula: see text]2.5[Formula: see text]V supply voltage. Moreover, the chip area of the chaos generator is only 1.755[Formula: see text]mm2 including the testing pads, and it has a wide range of practical application prospects.