Low Voltage Low Power Fully Integrated Chaos Generator

2018 ◽  
Vol 27 (10) ◽  
pp. 1850155 ◽  
Author(s):  
Jie Jin ◽  
LV Zhao
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Low Voltage ◽  
Supply Voltage ◽  
Electronic Components ◽  
Ic Design ◽  
Chip Area ◽  
Fully Integrated ◽  
Chaos Generator ◽  
Wide Range

A low voltage low power fully integrated chaos generator is presented in this paper. Comparing with the conventional off-the-shelf electronic components-based chaos generators, the designed circuit is fully integrated, and it achieves lower supply voltage, lower power dissipation and smaller chip area. The proposed fully integrated chaos generator is verified with GlobalFoundries 0.18[Formula: see text][Formula: see text]m CMOS 1P6M RF process using Cadence IC Design Tools. The simulation results demonstrate that the fully integrated chaos generator consumes only 17[Formula: see text]mW from [Formula: see text]2.5[Formula: see text]V supply voltage. Moreover, the chip area of the chaos generator is only 1.755[Formula: see text]mm2 including the testing pads, and it has a wide range of practical application prospects.

scholarly journals Fully Integrated Memristor and Its Application on the Scroll-Controllable Hyperchaotic System

Complexity ◽  
2019 ◽  
Vol 2019 ◽  
pp. 1-8 ◽  
Author(s):  
Jie Jin ◽  
Li Cui
Keyword(s):  
Power Dissipation ◽  
Supply Voltage ◽  
Nonlinear Function ◽  
Cmos Process ◽  
Hyperchaotic System ◽  
Single Chip ◽  
Ic Design ◽  
Chip Area ◽  
Fully Integrated ◽  
Memristor Emulator

In this paper, a fully integrated memristor emulator using operational amplifiers (OAs) and analog multipliers is simulated. Based on the fully integrated memristor, a scroll-controllable hyperchaotic system is presented. By controlling the nonlinear function with programmable switches, the memristor-based hyperchaotic system achieves controllable scroll numbers. Moreover, the memristor-based hyperchaotic system is fully integrated in one single chip, and it achieves lower supply voltage, lower power dissipation, and smaller chip area. The fully integrated memristor and memristor-based hyperchaotic system are verified with the GlobalFoundries’ 0.18 μm CMOS process using Cadence IC Design Tools. The postlayout simulation results demonstrate that the memristor-based fully integrated hyperchaotic system consumes 90.5 mW from ±2.5 V supply voltage and it takes a compact chip area of 1.8 mm2.

scholarly journals Comparative analysis of SRAM cell with leakage power reduction approaches

2018 ◽  
Vol 7 (2.7) ◽  
pp. 863
Author(s):  
Damarla Paradhasaradhi ◽  
Kollu Jaya Lakshmi ◽  
Yadavalli Harika ◽  
Busa Ravi Teja Sai ◽  
Golla Jayanth Krishna
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Low Voltage ◽  
Power Saving ◽  
Vital Role ◽  
Power Reduction ◽  
Leakage Power ◽  
Access Time ◽  
Chip Area ◽  
Sram Cell

In deep sub-micron technologies, high number of transistors is mounted onto a small chip area where, SRAM plays a vital role and is considered as a major part in many VLSI ICs because of its large density of storage and very less access time. Due to the demand of low power applications the design of low power and low voltage memory is a demanding task. In these memories majority of power dissipation depends on leakage power. This paper analyzes the basic 6T SRAM cell operation. Here two different leakage power reduction approaches are introduced to apply for basic 6T SRAM. The performance analysis of basic SRAM cell, SRAM cell using drowsy-cache approach and SRAM cell using clamping diode are designed at 130nm using Mentor Graphics IC Studio tool. The proposed SRAM cell using clamping diode proves to be a better power reduction technique in terms of power as compared with others SRAM structures. At 3.3V, power saving by the proposed SRAM cell is 20% less than associated to basic 6T SRAM Cell.

scholarly journals TIQ Flash ADC Design using a Low Power Multiplier Based Encoder

2019 ◽  
Vol 8 (2S2) ◽  
pp. 226-229
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Low Voltage ◽  
Supply Voltage ◽  
Power Supply Voltage ◽  
Large Power ◽  
Flash Adc ◽  
Analog To Digital ◽  
Tiq Comparator ◽  
The Impact

Threshold Inverter Quantization (TIQ) for applications of system-on-chip (SoC) depending on CMOS flash analog-to-digital converter (ADC). The TIQ technique which uses two cascaded CMOS inverters as a voltage comparator. However, this TIQ method must be created to meet the latest SoC trends, which force ADCs to be integrated with another electronic circuit on the chip and focus on low-power and low-voltage applications. TIQ comparator reduced the impact of variations in the process, temperature, and power supply voltage. Therefore, we obtained a higher TIQ flash ADC speed and resolution. TIQ flash ADC reduced / managed power dissipation. We obtain large power savings by managing the power dissipation in the comparator. Furthermore, the new comparator has a huge benefit in power dissipation and noise rejection comparative to the TIQ comparator [1]. The findings indicate that the TIQ flash ADC based on Modied mux attain heavy-speed transformation and has a tiny size, low-power dissipation and operation of lowvoltage compared to another flash ADCs.

scholarly journals A Low-Voltage, Low-Power Reconfigurable Current-Mode Softmax Circuit for Analog Neural Networks

Electronics ◽  
2021 ◽  
Vol 10 (9) ◽  
pp. 1004
Author(s):  
Massimo Vatalaro ◽  
Marco Lanuzza ◽  
Felice Crupi ◽  
Tatiana Moposita ◽  
Lionel Trojman ◽  
...  
Keyword(s):  
Low Power ◽  
Modular Design ◽  
Low Voltage ◽  
Supply Voltage ◽  
Current Mode ◽  
Cmos Technology ◽  
Chip Area ◽  
Analog Implementation ◽  
Efficient Option ◽  
P Type

This paper presents a novel low-power low-voltage analog implementation of the softmax function, with electrically adjustable amplitude and slope parameters. We propose a modular design, which can be scaled by the number of inputs (and of corresponding outputs). It is composed of input current–voltage linear converter stages (1st stages), MOSFETs operating in a subthreshold regime implementing the exponential functions (2nd stages), and analog divider stages (3rd stages). Each stage is only composed of p-type MOSFET transistors. Designed in a 0.18 µm CMOS technology (TSMC), the proposed softmax circuit can be operated at a supply voltage of 500 mV. A ten-input/ten-output realization occupies a chip area of 2570 µm2 and consumes only 3 µW of power, representing a very compact and energy-efficient option compared to the corresponding digital implementations.

scholarly journals A REVIEW OF LOW VOLTAGE AND LOW POWER CMOS ADDERS USING VLSI DESIGN IN VERILOG/VHDL

2021 ◽  
Vol 6 (3) ◽  
Author(s):  
Lokesh S
Keyword(s):  
Low Power ◽  
Threshold Voltage ◽  
Power Dissipation ◽  
Low Voltage ◽  
Supply Voltage ◽  
Vlsi Design ◽  
Research Field ◽  
Look Ahead ◽  
Threshold Voltages ◽  
Ripple Carry Adder

The dominant portion of power dissipation in CMOS adder circuits, due to logic transitions, varies as the square of the supply, significant savings in power dissipation may be exacted by operating with reduced supply voltage. If the supply voltage is reduced while threshold voltage stays same, the noise margins will reduce. Addition is a crucial process because it usually involve carry ripple steps which must propagate a carry signal from each bit to it’s higher bit position. This results in a substantial circuit delay. The adder which lies in the crucial delay path will effectively determine the system overall speed. To improve noise margins, the threshold voltages must also be made smaller. However subthreshold leakage current increases exponentially when threshold voltage is reduced. The higher static dissipation may then offset the reduction in transitions portion of the dissipation. Hence the devices needed to have threshold voltages that maximizes the net reduction in the dissipation. Addition is an obligatory operation that is crucial to processing the fundamental arithmetic operations. Due to the potential versatility of adders in this contemporary research field, the existing adders and adder designs currently intended for future low voltage and low power environments. This can be achieved by the CMOS adders namely Parallel Adder, Ripple Carry Adder(RCA), Carry Look Ahead Adder(CLA), Carry Select Adder(CSL), Carry Save Adder(CSA), Carry Skip Adder(CSK), Conditional Sum Adder(COS).

scholarly journals Design of Low Power Memory Architecture using 10t Sram Array

2019 ◽  
Vol 8 (4) ◽  
pp. 10650-10653
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Low Voltage ◽  
Supply Voltage ◽  
Random Access ◽  
Total Power ◽  
Access Time ◽  
Stable Operation ◽  
Sram Cell ◽  
Sram Design

The main aim of electronics is to design low power devices due to the prevalent usage of powered gadget. Ultra low voltage operation of memory cells has become a subject of a lot of interest because of its applications in terribly low energy computing. The stable operation of static random access memory (SRAM) is important for the success of low voltage SRAM and it is achieved by parameter variations of scaled technologies. The power consumption and access time of the SRAM is also a complex parameter due to the unavoidable switching activities of the number of transistors used for different blocks like, SRAM cell, access transistors, pre-charge circuit, sense amplifier and decoders. It has been shown that conventional 6T SRAM fail to achieve low power and delay operation. The proposed 10T SRAM design gives an approach towards the hold power dissipation. The designed circuit has 10 transistors out of that 2 transistors are used as sleep transistor. The sleep transistors are used as switches. Such as header and footer switches and the switches are turned on during active mode of operations and turned off during idle or standby mode of operations. The designed SRAM cell also has conducting pMOS circuit, which can reduces the total power dissipation. The SRAM cell is simulated by using Cadence tool. A supply voltage of 1.8V is used which makes it enough for low power applications. The power obtained as 761.7mW, which reduces 15% of conventional 6T SRAM design. The delay obtained as 125.6ns, which reduces 45% of conventional 6T SRAM.

A Fully-Integrated D-Band Frequency Synthesizer in 0.13-μm SiGe BiCMOS

2015 ◽  
Vol 25 (01) ◽  
pp. 1640010
Author(s):  
Jin He ◽  
Yong-Zhong Xiong ◽  
Jiankang Li ◽  
Muthukumaraswamy Annamalai Arasu ◽  
Yue Ping Zhang
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Frequency Synthesizer ◽  
Frequency Multiplier ◽  
Band Frequency ◽  
Chip Area ◽  
Fully Integrated ◽  
Bicmos Technology ◽  
Sige Bicmos ◽  
Low Power Dissipation

This paper presents a fully-integrated D-band frequency synthesizer (FS) in 0.13-[Formula: see text]m SiGe BiCMOS technology. The proposed FS consists of a 20-GHz phase-locked loop (PLL) and a frequency multiplier including a doubler ([Formula: see text][Formula: see text]2) and a quadrupler ([Formula: see text][Formula: see text]4). The FS generates the D-band output signals from 164.08 to 166.19[Formula: see text]GHz. At 166.19[Formula: see text]GHz, the measured phase noises (PN) at 100-kHz and 1-MHz offset frequencies are [Formula: see text]54.07[Formula: see text]dBc/Hz and [Formula: see text]72.29[Formula: see text]dBc/Hz, respectively. The proposed FS achieves the low power dissipation of around 110[Formula: see text]mW and the chip area is [Formula: see text] including all testing pads. The FS has great potential to be used for low-power D-band applications.

Low Voltage Low Power Folded Mixer for S-Band Wireless Applications

Frequenz ◽  
2014 ◽  
Vol 68 (11-12) ◽  
Author(s):  
Shiqiang Chen ◽  
Junfeng Wang
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Intermediate Frequency ◽  
Local Oscillator ◽  
Conversion Gain ◽  
Chip Area ◽  
Wireless Applications ◽  
Dc Power ◽  
Rf Signal

AbstractThis paper describes a low voltage low power (LV-LP) folded mixer for S-band wireless applications. The proposed mixer could convert a 10 MHz intermediate frequency (IF) signal to a 2.4 GHz RF signal with a local oscillator (LO) power of 0 dBm at 2.39 GHz. The comparison with the previous reported mixers shows that the proposed mixer has the advantages of lower voltage, lower power consumption and higher conversion gain than most of the other works. Simulation results demonstrate that the mixer a remarkable conversion gain of 10.5 dB while consuming only 0.65 mW DC power from a 0.8 V supply voltage. The input-referred third-order intercept point (IIP3) of the mixer is 3.75 dBm, and the chip area is only 0.525 mm

A Low Power High Gain CMOS LNA with Multiple-Feedback Network for Low Voltage UWB Receiver

2016 ◽  
Vol 25 (06) ◽  
pp. 1650051 ◽  
Author(s):  
Lv Zhao ◽  
Chunhua Wang
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
High Gain ◽  
Low Noise ◽  
Common Source ◽  
Cmos Process ◽  
Chip Area ◽  
Feedback Network ◽  
Uwb Receiver

In this paper, a high gain low voltage low power Complementary Metal Oxide Semiconductor (CMOS) Low-noise Amplifier (LNA) using Chartered 0.18[Formula: see text][Formula: see text]m CMOS process for Ultra-wideband (UWB) receiver applications is presented. A novel multiple-feedback network constructed by the shunt feedback resistor with a transformer is adopted to realize desirable bandwidth extension and less chip area occupation in the common-source stage. All the cascaded transistors are configured by current-reuse structure and adjusted by forward body bias technique to further reduce supply voltage and power dissipation. The post-layout simulation results demonstrate that the proposed 3.4–10.1[Formula: see text]GHz UWB LNA accomplishes a maximum gain of 14.26[Formula: see text]dB with only 2.33[Formula: see text]mW power consumption at 0.8[Formula: see text]V supply voltage, while Noise Figure (NF) is 1.49–3.41[Formula: see text]dB and the chip area is 0.46[Formula: see text]mm2 including test pads (core area is 0.23[Formula: see text]mm2).

COMPOSITE TRANSISTOR CELL USING DYNAMIC BODY BIAS FOR HIGH GAIN AND LOW-VOLTAGE APPLICATIONS

2014 ◽  
Vol 23 (08) ◽  
pp. 1450108 ◽  
Author(s):  
VANDANA NIRANJAN ◽  
ASHWANI KUMAR ◽  
SHAIL BALA JAIN
Keyword(s):  
Low Power ◽  
Large Scale ◽  
Low Voltage ◽  
Supply Voltage ◽  
High Gain ◽  
Signal Frequency ◽  
Output Impedance ◽  
Self Cascode ◽  
Intrinsic Gain ◽  
Body Bias

In this work, a new composite transistor cell using dynamic body bias technique is proposed. This cell is based on self cascode topology. The key attractive feature of the proposed cell is that body effect is utilized to realize asymmetric threshold voltage self cascode structure. The proposed cell has nearly four times higher output impedance than its conventional version. Dynamic body bias technique increases the intrinsic gain of the proposed cell by 11.17 dB. Analytical formulation for output impedance and intrinsic gain parameters of the proposed cell has been derived using small signal analysis. The proposed cell can operate at low power supply voltage of 1 V and consumes merely 43.1 nW. PSpice simulation results using 180 nm CMOS technology from Taiwan Semiconductor Manufacturing Company (TSMC) are included to prove the unique results. The proposed cell could constitute an efficient analog Very Large Scale Integration (VLSI) cell library in the design of high gain analog integrated circuits and is particularly interesting for biomedical and instrumentation applications requiring low-voltage low-power operation capability where the processing signal frequency is very low.

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