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A Formal Approach to Confidentiality Verification in SoCs at the Register Transfer Level
Mapping Intimacies
◽
10.1109/dac18074.2021.9586248
◽
2021
◽
Author(s):
Johannes Muller
◽
Mohammad Rahmani Fadiheh
◽
Anna Lena Duque Anton
◽
Thomas Eisenbarth
◽
Dominik Stoffel
◽
...
Keyword(s):
Register Transfer Level
◽
Formal Approach
◽
Register Transfer
Download Full-text
Related Documents
Cited By
References
Standard for Verilog register transfer level synthesis
10.3403/30128339u
◽
2015
◽
Keyword(s):
Register Transfer Level
◽
Register Transfer
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Fault Modeling of Combinational and Sequential Circuits at Register Transfer Level
International Journal of VLSI Design & Communication Systems
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10.5121/vlsic.2011.2406
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2011
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Vol 2
(4)
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pp. 61-68
Author(s):
M S Suma
Keyword(s):
Fault Modeling
◽
Register Transfer Level
◽
Sequential Circuits
◽
Register Transfer
◽
Combinational And Sequential Circuits
Download Full-text
Incorporating the controller effects during register transfer level synthesis
Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC
◽
10.1109/edtc.1994.326916
◽
2002
◽
Cited By ~ 4
Author(s):
C. Ramachandran
◽
F.J. Kurdahi
Keyword(s):
Register Transfer Level
◽
Register Transfer
Download Full-text
A non-scan DFT method at register-transfer level to achieve complete fault efficiency
Proceedings of the 2000 conference on Asia South Pacific design automation - ASP-DAC '00
◽
10.1145/368434.368825
◽
2000
◽
Cited By ~ 12
Author(s):
Satoshi Ohtake
◽
Hiroki Wada
◽
Toshimitsu Masuzawa
◽
Hideo Fujiwara
Keyword(s):
Dft Method
◽
Register Transfer Level
◽
Register Transfer
Download Full-text
Test pattern generators for distributed and embedded built-in self-test at register transfer level
Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design
◽
10.1109/isqed.2001.915236
◽
2002
◽
Author(s):
V. Vorisek
Keyword(s):
Test Pattern
◽
Register Transfer Level
◽
Register Transfer
◽
Self Test
◽
Built In Self Test
◽
Pattern Generators
Download Full-text
A Register Transfer Level Approach for Intermittent Semi-Concurrent Error Detection
2010 2nd International Conference on E-business and Information System Security
◽
10.1109/ebiss.2010.5473579
◽
2010
◽
Author(s):
Donghu Yang
◽
Jianhui Jiang
◽
Jie Yin
◽
Jipeng Huang
Keyword(s):
Error Detection
◽
Register Transfer Level
◽
Concurrent Error Detection
◽
Register Transfer
Download Full-text
Efficient Digital System Design Methodology with SystemC Register Transfer Level Modeling
IEEE SoutheastCon, 2004. Proceedings.
◽
10.1109/secon.2004.1287966
◽
2004
◽
Author(s):
M.C. Zabawa
◽
S.V. Wunnava
Keyword(s):
System Design
◽
Design Methodology
◽
Register Transfer Level
◽
Digital System
◽
Register Transfer
◽
Digital System Design
Download Full-text
Register-Transfer Level Hardware Description with SystemC
The VLSI Handbook, Second Edition - Electrical Engineering Handbook
◽
10.1201/9781420005967.ch89
◽
2006
◽
pp. 89-1-89-31
Author(s):
Zainalabedin Navabi
◽
Shahrzad Mirkhani
Keyword(s):
Register Transfer Level
◽
Register Transfer
◽
Hardware Description
Download Full-text
System-on-a-Chip (SoC) based Hardware Acceleration in Register Transfer Level (RTL) Design
10.25148/etd.fi13042902
◽
2012
◽
Cited By ~ 1
Author(s):
Xinwei Niu
Keyword(s):
Hardware Acceleration
◽
Register Transfer Level
◽
Register Transfer
◽
Rtl Design
◽
System On A Chip
Download Full-text
Property Driven Design based Verification for Register Transfer Level Hardware
2021 6th International Conference on Communication and Electronics Systems (ICCES)
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10.1109/icces51350.2021.9489148
◽
2021
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Author(s):
Aarthi R
◽
Aishwarya C
◽
Akash M U
◽
Krupasankar P
◽
Yadukrishnan G
◽
...
Keyword(s):
Register Transfer Level
◽
Register Transfer
Download Full-text
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