DRY FILM PHOTORESIST APPLICATION TO A PRINTED CIRCUIT BOARD (PCB) USING A MASKLESS PHOTOLITHOGRAPHY METHOD

This paper offers an alternative method of making PCB routing using a negative dry film photoresist and a maskless photolithography method. The objective of this research is to determine the correct parameters for the process of making PCB design easier, cheaper and safer.Electronic circuit design was created on a laptop or PC using Autodesk EAGLE software with a combination of result is black and blue light color. PCB routing design was inserted into a PowerPoint slide to display on a commercial Digital Light Processing (DLP) projector. Nomodifications were made to a projector, which was mounted directly on a stand with a downwardfacing position. The projector lamp replaced an ultraviolet or X-ray source during the exposureprocess, exposing PCB coated in negative dry film photoresist. After the exposure process, the PCB was inserted into the developer solution, causing the blue light irradiated part to remain while the blackened sections dissolved. The PCB was then added to an etching solution to scrape the copper unprotected by the photoresist. The PCB was finally soaked in a remover solution to remove the photoresist. Once complete, the process generated a laptop-designed PCB routing. Electrical lines can be created using this method with a size of 100 µm and a lane edge deviation of 5 µm. The goal of research to make PCB routing cheaper, easier and safer was achieved. Evidenced by the installation of electronic components and then tested, the results are all components function well.

Placement of the decoupling capacitors under the BGA component

The efficiency of PCB routing is determined by the quality of the placement of electronic components on the board. The placement of the two-port elements under the BGA-component, although being a local task, is labor-intensive. This paper describes the technique of arranging the decoupling capacitors under the BGA component, including determining the position of the capacitor relative to the matrix pins, positioning and orientation of the capacitor near the equipotential pin of the chip and the sequence of capacitors placement. Formulas that allow estimating the possibility or impossibility of placing the two-port element in a specific position are given. The technique is currently being implemented in the domestic CAD system TopoR.