2015 Conference on Design and Architectures for Signal and Image Processing (DASIP)
Latest Publications

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37

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5

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Published By IEEE

9781467377386

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Fast and efficient signals recovery for deterministic compressive sensing: Applications to biosignals

2015 Conference on Design and Architectures for Signal and Image Processing (DASIP) ◽

10.1109/dasip.2015.7367263 ◽

2015 ◽

Author(s):

Andrianiaina Ravelomanantsoa ◽

Hassan Rabah ◽

Amar Rouane

Keyword(s):

Compressive Sensing ◽

Sensing Applications

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Implementation of IEEE-802.11a/g receiver blocks on a coarse-grained reconfigurable array

2015 Conference on Design and Architectures for Signal and Image Processing (DASIP) ◽

10.1109/dasip.2015.7367254 ◽

2015 ◽

Author(s):

Sajjad Nouri ◽

Waqar Hussain ◽

Jari Nurmi

Keyword(s):

Coarse Grained ◽

Ieee 802.11A ◽

Reconfigurable Array

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Session 2: Processing architectures for biomedical signal and image processing

2015 Conference on Design and Architectures for Signal and Image Processing (DASIP) ◽

10.1109/dasip.2015.7367242 ◽

2015 ◽

Author(s):

Pierre Langlois

Keyword(s):

Image Processing ◽

Biomedical Signal ◽

Signal And Image Processing ◽

Processing Architectures

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Exploring custom heterogeneous MPSoCs for real-time neural signal decoding

2015 Conference on Design and Architectures for Signal and Image Processing (DASIP) ◽

10.1109/dasip.2015.7367243 ◽

2015 ◽

Author(s):

Paolo Meloni ◽

Giuseppe Tuveri ◽

Danilo Pani ◽

Luigi Raffo ◽

Francesca Palumbo

Keyword(s):

Real Time ◽

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Session 6: Parallel implementations of HEVC and FFT for embedded multi-/manycore systems

2015 Conference on Design and Architectures for Signal and Image Processing (DASIP) ◽

10.1109/dasip.2015.7367267 ◽

2015 ◽

Author(s):

Karol Desnos

Keyword(s):

Parallel Implementations

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MATIP: A dynamic hardware task integration platform for Multiprocessing Reconfigurable System on Chip

2015 Conference on Design and Architectures for Signal and Image Processing (DASIP) ◽

10.1109/dasip.2015.7367261 ◽

2015 ◽

Keyword(s):

System On Chip ◽

Integration Platform ◽

Reconfigurable System ◽

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Demonstrating an FPGA implementation of a full HD real-time HEVC decoder with memory optimizations for range extensions support

2015 Conference on Design and Architectures for Signal and Image Processing (DASIP) ◽

10.1109/dasip.2015.7367247 ◽

2015 ◽

Author(s):

Benno Stabernack ◽

Jan Moller ◽

Jan Hahlbeck ◽

Jens Brandenburg

Keyword(s):

Real Time ◽

Fpga Implementation ◽

Memory Optimizations ◽

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BM3D image denoising using heterogeneous computing platforms

2015 Conference on Design and Architectures for Signal and Image Processing (DASIP) ◽

10.1109/dasip.2015.7367257 ◽

2015 ◽

Author(s):

Sampsa Sarjanoja ◽

Jani Boutellier ◽

Jari Hannuksela

Keyword(s):

Image Denoising ◽

Heterogeneous Computing ◽

Computing Platforms

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FPGA based system for real-time structure from motion computation

2015 Conference on Design and Architectures for Signal and Image Processing (DASIP) ◽

10.1109/dasip.2015.7367241 ◽

2015 ◽

Author(s):

Mateusz Komorkiewicz ◽

Tomasz Kryjak ◽

Katarzyna Chuchacz-Kowalczyk ◽

Pawel Skruch ◽

Marek Gorgon

Keyword(s):

Real Time ◽

Structure From Motion ◽

Time Structure ◽

Motion Computation

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Hardware implementation of a soft cancellation decoder for polar codes

2015 Conference on Design and Architectures for Signal and Image Processing (DASIP) ◽

10.1109/dasip.2015.7367252 ◽

2015 ◽

Author(s):

Guillaume Berhault ◽

Camille Leroux ◽

Christophe Jego ◽

Dominique Dallet

Keyword(s):

Hardware Implementation ◽

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