Glitch Power Reduction via Clock Skew Scheduling

Resonant clocking technologies provide clock networks with improved frequency, jitter and power dissipation characteristics, however, often require novel automation routines. Resonant rotary clocking technology, for instance, entails multi-phase and nonzero clock skew operation and supports latch-based design. This paper studies the effects of multi-phase synchronization schemes on the minimum clock period for rotary-clock-synchronized circuits, which necessitate the application of clock skew scheduling and employ level-sensitive registers. In experimentation, single, dual, three- and four-phase clocking schemes generated by rotary clock synchronization are applied to a suite of level-sensitive-transformed ISCAS'89 benchmarks. Average clock period improvements of 30.3%, 24.8%, 17.7% and 12.0%, respectively, are observed on average compared to the flip-flop based, zero clock skew circuits. As the number of clock phases increases, smaller improvements are observed due to lesser overall effectiveness of the complementary effects of clock skew scheduling and time borrowing. It is shown, however, that for some circuits (23% of the benchmarks), multi-phase synchronization leads to significant performance benefits in operating frequency.

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Clock Skew Scheduling of Level-Sensitive Circuits

Timing Optimization Through Clock Skew Scheduling ◽

10.1007/978-0-387-71056-3_6 ◽

2008 ◽

pp. 97-120

Keyword(s):

Clock Skew ◽

Clock Skew Scheduling

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Clock Skew Scheduling in Rotary Clocking Technology

Timing Optimization Through Clock Skew Scheduling ◽

10.1007/978-0-387-71056-3_10 ◽

2008 ◽

pp. 183-204

Keyword(s):

Clock Skew ◽

Clock Skew Scheduling

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STATISTICAL TIMING ANALYSIS OF THE CLOCK PERIOD IMPROVEMENT THROUGH CLOCK SKEW SCHEDULING

Journal of Circuits System and Computers ◽

10.1142/s0218126611007669 ◽

2011 ◽

Vol 20 (05) ◽

pp. 881-898 ◽

Cited By ~ 1

Author(s):

SHANNON M. KURTAS ◽

BARIS TASKIN

Keyword(s):

Timing Analysis ◽

Process Variations ◽

Clock Signal ◽

Static Timing Analysis ◽

Clock Skew ◽

Clock Period ◽

Static Timing ◽

Statistical Static Timing Analysis ◽

Clock Skew Scheduling ◽

Zero Skew

Statistical static timing analysis (SSTA) methods, which model process variations statistically as probability distribution function rather than deterministically, have been thoroughly performed on traditional zero clock skew circuits. In the traditional zero clock skew circuits, the synchronizing clock signal is designed to arrive in phase with respect to each register. However, designers will often schedule the clock skew to different registers in order to decrease the minimum clock period of the entire circuit. Clock skew scheduling imparts very different timing constraints that are based, in part, on the topology of the circuit. In this paper, SSTA is applied to nonzero clock skew circuits in order to determine the accuracy improvement relative to their zero skew counterparts, and also to assess how the results of skew scheduling might be impacted with more accurate statistical modeling. For 99.7% timing yield (3σ variation), SSTA is observed to improve the accuracy, and therefore increase the timing margin, of nonzero clock skew circuits by up to 2.5×, and on average by 1.3×, the amount seen by zero skew circuits.

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