Linear Compositional Delay Model for the Timing Analysis of Sub-Powered Combinational Circuits

2014 ◽  
Author(s):  
Jiaoyan Chen ◽  
Christian Spagnol ◽  
Satish Grandhi ◽  
Emanuel Popovici ◽  
Sorin Cotofana ◽  
...  
Keyword(s):  
Timing Analysis ◽  
Delay Model ◽  
Combinational Circuits

scholarly journals Improving Analytical Delay Modelingfor CMOS Inverters

2015 ◽  
Vol 10 (2) ◽  
pp. 123-134
Author(s):  
Felipe S. Marranghello ◽  
André I. Reis ◽  
Renato P. Ribas
Keyword(s):  
Integrated Circuits ◽  
Timing Analysis ◽  
Channel Length ◽  
Delay Model ◽  
Digital Integrated Circuits ◽  
Cmos Inverter ◽  
Worst Case ◽  
Average Value ◽  
Coupling Capacitance ◽  
Novel Approach

Analytical methods for gate delay estimation are very useful to speedup timing analysis of digital integrated circuits. This work presents a novel approach to analytically estimate the CMOS inverter delay. The proposed method considers the influence of input slope, output load and I/O coupling capacitance, as well as relevant effects such as channel length modulation and drain induced barrier lowering. Experimental results are on good agreement with HSPICE simulations, showing significant accuracy improvement compared to published related work. The delay model error has an average value of 3%, and the worst case error is smaller than 10%.

Symbolic timing analysis and resynthesis for low power of combinational circuits containing false paths

1997 ◽  
Vol 16 (10) ◽  
pp. 1101-1115 ◽  
Author(s):  
R.I. Bahar ◽  
Hyunwoo Cho ◽  
G.D. Hachtel ◽  
E. Macii ◽  
F. Somenzi
Keyword(s):  
Low Power ◽  
Timing Analysis ◽  
Combinational Circuits ◽  
False Paths
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