2008 IEEE International High Level Design Validation and Test Workshop
Latest Publications

TOTAL DOCUMENTS

44

(FIVE YEARS 0)

H-INDEX

3

(FIVE YEARS 0)

Published By IEEE

9781424429226

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Applications of decorator and observer design patterns in functional verification

2008 IEEE International High Level Design Validation and Test Workshop ◽

10.1109/hldvt.2008.4695867 ◽

2008 ◽

Author(s):

Farzin Karimi

Keyword(s):

Design Patterns ◽

Observer Design ◽

Functional Verification

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Timing verification of distributed network systems at higher levels of abstraction

2008 IEEE International High Level Design Validation and Test Workshop ◽

10.1109/hldvt.2008.4695884 ◽

2008 ◽

Author(s):

Hassan Hatefi-Ardakani ◽

Amir Masoud Gharehbaghi ◽

Shaahin Hessabi

Keyword(s):

Distributed Network ◽

Timing Verification ◽

Levels Of Abstraction ◽

Network Systems

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Panel: SoC power management implications on validation and testing

2008 IEEE International High Level Design Validation and Test Workshop ◽

10.1109/hldvt.2008.4695890 ◽

2008 ◽

Author(s):

Bhanu Kapoor ◽

John Goodenough ◽

Shankar Hemmady ◽

Shireesh Verma ◽

Manuel A. d'Abreu ◽

...

Keyword(s):

Power Management ◽

Management Implications

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A HW/SW co-simulation framework for the verification of multi-CPU systems

2008 IEEE International High Level Design Validation and Test Workshop ◽

10.1109/hldvt.2008.4695888 ◽

2008 ◽

Author(s):

S. Cordibella ◽

F. Fummi ◽

G. Perbellini ◽

D. Quaglia

Keyword(s):

Simulation Framework

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Temporal parallel gate-level timing simulation

2008 IEEE International High Level Design Validation and Test Workshop ◽

10.1109/hldvt.2008.4695886 ◽

2008 ◽

Author(s):

Dusung Kim ◽

Maciej Ciesielski ◽

Kyuho Shim ◽

Seiyang Yang

Keyword(s):

Timing Simulation

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On Chip Instrument application to SoC analysis

2008 IEEE International High Level Design Validation and Test Workshop ◽

10.1109/hldvt.2008.4695879 ◽

2008 ◽

Author(s):

Neal Stollon

Keyword(s):

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On dynamic switching of navigation for semi-formal design validation

2008 IEEE International High Level Design Validation and Test Workshop ◽

10.1109/hldvt.2008.4695873 ◽

2008 ◽

Author(s):

Ankur Parikh ◽

Michael S. Hsiao

Keyword(s):

Design Validation ◽

Dynamic Switching ◽

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Session 2: Test

2008 IEEE International High Level Design Validation and Test Workshop ◽

10.1109/hldvt.2008.4695868 ◽

2008 ◽

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Injecting intermittent faults for the dependability validation of commercial microcontrollers

2008 IEEE International High Level Design Validation and Test Workshop ◽

10.1109/hldvt.2008.4695899 ◽

2008 ◽

Author(s):

D. Gil ◽

L.J. Saiz ◽

J. Gracia ◽

J.C. Baraza ◽

P.J. Gil

Keyword(s):

Intermittent Faults

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Test and validation of a non-deterministic system — True Random Number Generator

2008 IEEE International High Level Design Validation and Test Workshop ◽

10.1109/hldvt.2008.4695881 ◽

2008 ◽

Author(s):

Kapila Udawatta ◽

Mehdi Ehsanian ◽

Sergey Maidanov ◽

Surya Musunuri

Keyword(s):

Random Number ◽

Random Number Generator ◽

Deterministic System ◽

Number Generator ◽

True Random Number Generator

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