IEEE/ACM International Conference on Computer-Aided Design
Latest Publications

TOTAL DOCUMENTS

130

(FIVE YEARS 0)

H-INDEX

(FIVE YEARS 0)

Published By IEEE

0818664177

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Selecting Partial Scan Flip-flops For Circuit Partitioning

IEEE/ACM International Conference on Computer-Aided Design ◽

10.1109/iccad.1994.629890 ◽

2005 ◽

Cited By ~ 1

Author(s):

T. Ono

Keyword(s):

Circuit Partitioning ◽

Partial Scan

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A New Global Routing Algorithm For FPGAs

IEEE/ACM International Conference on Computer-Aided Design ◽

10.1109/iccad.1994.629817 ◽

2005 ◽

Cited By ~ 2

Author(s):

Yao-Wen Chang ◽

S. Thakur ◽

Kai Zhu ◽

D.F. Wong

Keyword(s):

Routing Algorithm ◽

Global Routing

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Risa: Accurate And Efficient Placement Routability Modeling

IEEE/ACM International Conference on Computer-Aided Design ◽

10.1109/iccad.1994.629897 ◽

2005 ◽

Author(s):

Chih-liang Eric Cheng

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Timing Uncertainty Analysis For Time-of-flight Systems

IEEE/ACM International Conference on Computer-Aided Design ◽

10.1109/iccad.1994.629904 ◽

2005 ◽

Cited By ~ 1

Author(s):

J.R. Feehrer ◽

H.F. Jordan

Keyword(s):

Uncertainty Analysis ◽

Time Of Flight ◽

Timing Uncertainty

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Efficient Implementation Of Retiming

IEEE/ACM International Conference on Computer-Aided Design ◽

10.1109/iccad.1994.629770 ◽

2005 ◽

Cited By ~ 17

Author(s):

N. Shenoy ◽

R. Rudell

Keyword(s):

Efficient Implementation

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On Error Correction In Macro-based Circuits

IEEE/ACM International Conference on Computer-Aided Design ◽

10.1109/iccad.1994.629877 ◽

2005 ◽

Cited By ~ 5

Author(s):

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Error Correction

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Incremental Synthesis

IEEE/ACM International Conference on Computer-Aided Design ◽

10.1109/iccad.1994.629736 ◽

2005 ◽

Cited By ~ 21

Author(s):

D. Brand

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Multi-level Logic Optimization By Implication Analysis

IEEE/ACM International Conference on Computer-Aided Design ◽

10.1109/iccad.1994.629735 ◽

2005 ◽

Cited By ~ 36

Author(s):

W. Kunz

Keyword(s):

Logic Optimization ◽

Multi Level

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Fast Timing Simulation Of Transient Faults In Digital Circuits

IEEE/ACM International Conference on Computer-Aided Design ◽

10.1109/iccad.1994.629902 ◽

2005 ◽

Cited By ~ 7

Author(s):

A. Dharchoudhury ◽

S.M. Kang ◽

H. Cha ◽

J.H. Patel

Keyword(s):

Digital Circuits ◽

Transient Faults ◽

Fast Timing ◽

Timing Simulation

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Fault Detection And Input Stimulus Determination For The Testing Of Analog Integrated Circuits Based On Power-supply Current Monitoring

IEEE/ACM International Conference on Computer-Aided Design ◽

10.1109/iccad.1994.629866 ◽

2005 ◽

Cited By ~ 22

Author(s):

G. Gielen ◽

Zhihua Wang ◽

W. Sansen

Keyword(s):

Fault Detection ◽

Integrated Circuits ◽

Power Supply ◽

Analog Integrated Circuits ◽

Input Stimulus ◽

Supply Current ◽

Current Monitoring

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IEEE/ACM International Conference on Computer-Aided DesignLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Selecting Partial Scan Flip-flops For Circuit Partitioning

A New Global Routing Algorithm For FPGAs

Risa: Accurate And Efficient Placement Routability Modeling

Timing Uncertainty Analysis For Time-of-flight Systems

Efficient Implementation Of Retiming

On Error Correction In Macro-based Circuits

Incremental Synthesis

Multi-level Logic Optimization By Implication Analysis

Fast Timing Simulation Of Transient Faults In Digital Circuits

Fault Detection And Input Stimulus Determination For The Testing Of Analog Integrated Circuits Based On Power-supply Current Monitoring

IEEE/ACM International Conference on Computer-Aided Design
Latest Publications