Realization of combinatorial optimization of small-scale S-box

This method describes a new technology for combinatorial logic optimization in detail, which can combine multiple criteria to reduce the hardware implementation area of the S-box. This technique can be achieved in two steps. The first is to optimize the non-linear part of the S-box. According to the optimization criterion of multiplication complexity, the quality of the S-box nonlinear part optimization can be judged, and the realization of the S-box with the smallest multiplication complexity can be obtained. The second step is to optimize the linear part of the S-box, and optimize on the basis of the results of the first step, focusing on reducing the number of XOR gates, and the optimization is performed through a heuristic-based algorithm. The above combinatorial logic optimization technology can be applied to any small S-box (5 × 5 and below). Finally, the S-box of PRESENT algorithm and CTC2 algorithm are used as examples to illustrate the optimization effect, and the optimal realization under the minimum AND gate condition is obtained.