1997 IEEE Workshop on Signal Processing Systems. SiPS 97 Design and Implementation formerly VLSI Signal Processing
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TOTAL DOCUMENTS

56

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9

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Published By IEEE

0780338065

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Implementation of the 2D DCT using a Xilinx XC6264 FPGA

1997 IEEE Workshop on Signal Processing Systems. SiPS 97 Design and Implementation formerly VLSI Signal Processing ◽

10.1109/sips.1997.626344 ◽

2002 ◽

Author(s):

D.W. Trainor ◽

J.P. Heron ◽

R.F. Woods

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Implementation strategy of MPEG-2 audio decoder and efficient multichannel architecture

1997 IEEE Workshop on Signal Processing Systems. SiPS 97 Design and Implementation formerly VLSI Signal Processing ◽

10.1109/sips.1997.626147 ◽

2002 ◽

Author(s):

Tsung-Han Tsai ◽

Liang-Gee Chen ◽

Ruei-Xi Chen

Keyword(s):

Implementation Strategy ◽

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System-level power exploration for MPEG-2 decoder on embedded cores: a systematic approach

1997 IEEE Workshop on Signal Processing Systems. SiPS 97 Design and Implementation formerly VLSI Signal Processing ◽

10.1109/sips.1997.626277 ◽

2002 ◽

Author(s):

D. Moolenaar ◽

L. Nachtergaele ◽

F. Catthoor ◽

H. De Man

Keyword(s):

Systematic Approach ◽

System Level ◽

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Optimum primitive polynomials for low-area low-power finite field semi-systolic multipliers

1997 IEEE Workshop on Signal Processing Systems. SiPS 97 Design and Implementation formerly VLSI Signal Processing ◽

10.1109/sips.1997.626273 ◽

2002 ◽

Author(s):

L. Song ◽

K.K. Parhi

Keyword(s):

Finite Field ◽

Low Power ◽

Low Area ◽

Primitive Polynomials

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Heterogeneous reconfigurable systems

1997 IEEE Workshop on Signal Processing Systems. SiPS 97 Design and Implementation formerly VLSI Signal Processing ◽

10.1109/sips.1997.625684 ◽

2002 ◽

Author(s):

J.M. Rabaey ◽

A. Abnous ◽

Y. Ichikawa ◽

K. Seno ◽

M. Wan

Keyword(s):

Reconfigurable Systems

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Design and implementation of a complex multiplier using distributed arithmetic

1997 IEEE Workshop on Signal Processing Systems. SiPS 97 Design and Implementation formerly VLSI Signal Processing ◽

10.1109/sips.1997.626125 ◽

2002 ◽

Author(s):

M. Karlsson ◽

M. Vesterbacka ◽

L. Wanhammar

Keyword(s):

Distributed Arithmetic ◽

Design And Implementation ◽

Complex Multiplier

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A programmable VLC core architecture for video compression DSP

1997 IEEE Workshop on Signal Processing Systems. SiPS 97 Design and Implementation formerly VLSI Signal Processing ◽

10.1109/sips.1997.626321 ◽

2002 ◽

Author(s):

Y. Fukuzawa ◽

K. Hasegawa ◽

H. Hanaki ◽

E. Iwata ◽

T. Yamazaki

Keyword(s):

Video Compression

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Multithreaded systolic/SIMD DSP array processor-MUS2DAP

1997 IEEE Workshop on Signal Processing Systems. SiPS 97 Design and Implementation formerly VLSI Signal Processing ◽

10.1109/sips.1997.626309 ◽

2002 ◽

Author(s):

R. Sernec ◽

M. Zajc ◽

J.F. Tasic

Keyword(s):

Array Processor ◽

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Optimising designs for hardware compilation to FPGAs

1997 IEEE Workshop on Signal Processing Systems. SiPS 97 Design and Implementation formerly VLSI Signal Processing ◽

10.1109/sips.1997.626342 ◽

2002 ◽

Author(s):

F.J. O'Reilly ◽

W.P. Marnane ◽

P.J. Murphy

Keyword(s):

Hardware Compilation

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On-line architecture for the S.Mallat algorithm

1997 IEEE Workshop on Signal Processing Systems. SiPS 97 Design and Implementation formerly VLSI Signal Processing ◽

10.1109/sips.1997.626114 ◽

2002 ◽

Author(s):

O. Nedjah ◽

M. Chihabe

Keyword(s):

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