2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC)
Latest Publications

TOTAL DOCUMENTS

136

(FIVE YEARS 0)

H-INDEX

(FIVE YEARS 0)

Published By IEEE

9781467326582, 9781467326575, 9781467326568

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Using asymmetric layer repair capability to reduce the cost of yield enhancement in 3D stacked memories

2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC) ◽

10.1109/vlsi-soc.2012.7332100 ◽

2012 ◽

Author(s):

M. Tauseef Rab ◽

Asad A. Bawa ◽

Nur A. Touba

Keyword(s):

Yield Enhancement ◽

The Cost

A new reliability evaluation methodology and its application to network-on-chip routers

2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC) ◽

10.1109/vlsi-soc.2012.6379041 ◽

2012 ◽

Cited By ~ 1

Author(s):

Hamed S. Kia ◽

Cristinel Ababei

Keyword(s):

Reliability Evaluation ◽

Network On Chip ◽

Evaluation Methodology ◽

On Chip

A novel elementary memristive system

2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC) ◽

10.1109/vlsi-soc.2012.7332080 ◽

2012 ◽

Author(s):

Fernando Corinto ◽

Alon Ascoli ◽

Marco Gilli

Keyword(s):

Memristive System

A general-transformation EWA view rendering engine for 1080p video in 130 nm CMOS

2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC) ◽

10.1109/vlsi-soc.2012.7332085 ◽

2012 ◽

Cited By ~ 1

Author(s):

Pierre Greisen ◽

Richard Emler ◽

Michael Schaffner ◽

Simon Heinzle ◽

Frank Gurkaynak

Keyword(s):

General Transformation ◽

Rendering Engine

Methodology for early estimation of hierarchical routing resources in 3D FPGAs

2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC) ◽

10.1109/vlsi-soc.2012.7332103 ◽

2012 ◽

Author(s):

Krishna Chaitanya Nunna ◽

Farhad Mehdipour ◽

Masayoshi Yoshimura ◽

Kazuaki Murakami

Keyword(s):

Hierarchical Routing

Low cost adjacent double error correcting code with complete elimination of miscorrection within a dispersion window for Multiple Bit Upset tolerant memory

2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC) ◽

10.1109/vlsi-soc.2012.6379048 ◽

2012 ◽

Cited By ~ 7

Author(s):

Avijit Dutta

Keyword(s):

Low Cost ◽

Error Correcting Code ◽

Complete Elimination

TamaRISC-CS: An ultra-low-power application-specific processor for compressed sensing

2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC) ◽

10.1109/vlsi-soc.2012.7332094 ◽

2012 ◽

Cited By ~ 5

Author(s):

Jeremy Constantin ◽

Ahmed Dogan ◽

Oskar Andersson ◽

Pascal Meinerzhagen ◽

Joachim Neves Rodrigues ◽

...

Keyword(s):

Compressed Sensing ◽

Low Power ◽

Ultra Low Power ◽

Power Application ◽

Application Specific

Low noise front-end amplifier design for medical ultrasound imaging applications

2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC) ◽

10.1109/vlsi-soc.2012.7332069 ◽

2012 ◽

Cited By ~ 1

Author(s):

Surya Sharma ◽

Trond Ytterdal

Keyword(s):

Ultrasound Imaging ◽

Low Noise ◽

Medical Ultrasound ◽

Medical Ultrasound Imaging ◽

Front End ◽

Amplifier Design

Force-Directed List Scheduling for Digital Microfluidic Biochips

2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC) ◽

10.1109/vlsi-soc.2012.6378997 ◽

2012 ◽

Cited By ~ 5

Author(s):

Kenneth O'Neal ◽

Daniel Grissom ◽

Philip Brisk

Keyword(s):

List Scheduling ◽

Microfluidic Biochips ◽

Digital Microfluidic

Reliability enhancement of power gating transistor under time dependent dielectric breakdown

2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC) ◽

10.1109/vlsi-soc.2012.7332099 ◽

2012 ◽

Author(s):

Hamid Mahmoodi

Keyword(s):

Dielectric Breakdown ◽

Time Dependent ◽

Power Gating ◽

Time Dependent Dielectric Breakdown ◽

Reliability Enhancement

2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Using asymmetric layer repair capability to reduce the cost of yield enhancement in 3D stacked memories

A new reliability evaluation methodology and its application to network-on-chip routers

A novel elementary memristive system

A general-transformation EWA view rendering engine for 1080p video in 130 nm CMOS

Methodology for early estimation of hierarchical routing resources in 3D FPGAs

Low cost adjacent double error correcting code with complete elimination of miscorrection within a dispersion window for Multiple Bit Upset tolerant memory

TamaRISC-CS: An ultra-low-power application-specific processor for compressed sensing

Low noise front-end amplifier design for medical ultrasound imaging applications

Force-Directed List Scheduling for Digital Microfluidic Biochips

Reliability enhancement of power gating transistor under time dependent dielectric breakdown

2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC)
Latest Publications