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A new reliability evaluation methodology and its application to network-on-chip routers
2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC)
◽
10.1109/vlsi-soc.2012.6379041
◽
2012
◽
Cited By ~ 1
Author(s):
Hamed S. Kia
◽
Cristinel Ababei
Keyword(s):
Reliability Evaluation
◽
Network On Chip
◽
Evaluation Methodology
◽
On Chip
Download Full-text
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Cited By
References
A new reliability evaluation methodology and its application to network-on-chip routers
2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC)
◽
10.1109/vlsi-soc.2012.7332112
◽
2012
◽
Author(s):
Hamed S. Kia
◽
Cristinel Ababei
Keyword(s):
Reliability Evaluation
◽
Network On Chip
◽
Evaluation Methodology
◽
On Chip
Download Full-text
Yield-oriented evaluation methodology of network-on-chip routing implementations
2009 International Symposium on System-on-Chip
◽
10.1109/socc.2009.5335667
◽
2009
◽
Cited By ~ 5
Author(s):
S. Rodrigo
◽
C. Hernandez
◽
J. Flich
◽
F. Silla
◽
J. Duato
◽
...
Keyword(s):
Network On Chip
◽
Evaluation Methodology
◽
On Chip
Download Full-text
Unified system level reliability evaluation methodology for multiprocessor Systems-on-Chip
2012 International Green Computing Conference (IGCC)
◽
10.1109/igcc.2012.6322282
◽
2012
◽
Cited By ~ 1
Author(s):
Alexandre Yasuo Yamamoto
◽
Cristinel Ababei
Keyword(s):
Reliability Evaluation
◽
System Level
◽
Evaluation Methodology
◽
Multiprocessor Systems
◽
Systems On Chip
◽
On Chip
Download Full-text
Real Time Network on Chip (NOC) Architecture with CDMA Techniques with Audio Decoders
Oct. 17-19, 2017 Dubai (UAE)
◽
10.15242/dirpub.dir1017020
◽
2018
◽
Keyword(s):
Real Time
◽
Network On Chip
◽
On Chip
Download Full-text
A congestion-aware routing algorithm for simplified mesh-of-tree architecture in network-on-chip designs
Artificial Intelligence and Industrial Application
◽
10.2495/aiia140551
◽
2015
◽
Author(s):
J. Fang
◽
L. Yu
◽
Z. Y. Leng
Keyword(s):
Routing Algorithm
◽
Network On Chip
◽
Tree Architecture
◽
On Chip
◽
Congestion Aware
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VLSI Design Of Low Energy Modeling For Network On Chip (NoC) Applications
i-manager’s Journal on Electronics Engineering
◽
10.26634/jele.5.1.3320
◽
2014
◽
Vol 5
(1)
◽
pp. 27-32
Author(s):
Jeeva Anusha
◽
◽
V. Thrimurthulu
◽
Keyword(s):
Vlsi Design
◽
Network On Chip
◽
Energy Modeling
◽
Low Energy
◽
On Chip
Download Full-text
Pre-allocated Path Based Low Latency Router Architecture for Network-on-chip
JOURNAL OF ELECTRONICS INFORMATION TECHNOLOGY
◽
10.3724/sp.j.1146.2012.00654
◽
2014
◽
Vol 35
(2)
◽
pp. 341-346
Author(s):
Xiao-fu Zheng
◽
Hua-xi Gu
◽
Yin-tang Yang
◽
Zhong-fan Huang
Keyword(s):
Network On Chip
◽
Low Latency
◽
Router Architecture
◽
On Chip
Download Full-text
Example Antenna and Link Performance for Wireless Network on Chip Applications
12th European Conference on Antennas and Propagation (EuCAP 2018)
◽
10.1049/cp.2018.0956
◽
2018
◽
Author(s):
W. Rayess
◽
D.W. Matolak
Keyword(s):
Wireless Network
◽
Network On Chip
◽
Link Performance
◽
On Chip
Download Full-text
An optimized path-setup method for mesh based Optical Network on Chip
2015 14th International Conference on Optical Communications and Networks (ICOCN)
◽
10.1109/icocn.2015.7203619
◽
2015
◽
Author(s):
Wei Tan
◽
Bowen Zhang
◽
Huaxi Gu
◽
Zheng Chen
Keyword(s):
Optical Network
◽
Network On Chip
◽
On Chip
Download Full-text
A Novel Scheme to Map Convolutional Networks to Network-on-Chip with Computing-In-Memory Nodes
2020 International SoC Design Conference (ISOCC)
◽
10.1109/isocc50952.2020.9332940
◽
2020
◽
Author(s):
Jiayi Liu
◽
Kejie Huang
Keyword(s):
Network On Chip
◽
Convolutional Networks
◽
On Chip
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