Proceedings of 7th International Conference on VLSI Design
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Data path testability evaluation via functional testability measures

Proceedings of 7th International Conference on VLSI Design ◽

10.1109/icvd.1994.282707 ◽

2002 ◽

Author(s):

M. Jamoussi ◽

B. Kaminska

Keyword(s):

Data Path ◽

Testability Measures

A 2K×1K space switch ASIC for use in digital exchanges

Proceedings of 7th International Conference on VLSI Design ◽

10.1109/icvd.1994.282695 ◽

2002 ◽

Author(s):

V. Keshava Murthy ◽

K. Madhu Kumar ◽

M.B. Vani ◽

D. Jagadish Kumar ◽

C.S. Mohan ◽

...

A methodology for architecture synthesis of cascaded IIR filters on TLU FPGAs

Proceedings of 7th International Conference on VLSI Design ◽

10.1109/icvd.1994.282690 ◽

2002 ◽

Author(s):

G.N. Rathna ◽

S.K. Nandy ◽

K. Parthasarathy

Keyword(s):

Iir Filters

An optimal design for parallel test generation based on circuit partitioning

Proceedings of 7th International Conference on VLSI Design ◽

10.1109/icvd.1994.282706 ◽

2002 ◽

Cited By ~ 1

Author(s):

Dong Xiang ◽

Dao-Zheng Wei

Keyword(s):

Optimal Design ◽

Test Generation ◽

Circuit Partitioning ◽

Parallel Test

An empirical study on the effects of physical design in high-level synthesis

Proceedings of 7th International Conference on VLSI Design ◽

10.1109/icvd.1994.282638 ◽

2002 ◽

Cited By ~ 1

Author(s):

P.K. Jha ◽

C. Ramachandran ◽

N.D. Dutt ◽

F.J. Kurdahi

Keyword(s):

Empirical Study ◽

Physical Design ◽

High Level Synthesis ◽

High Level

An efficient hybrid heuristic for the gate matrix layout problem in VLSI design

Proceedings of 7th International Conference on VLSI Design ◽

10.1109/icvd.1994.282686 ◽

2002 ◽

Author(s):

T. Bagchi ◽

S.K. Das

Keyword(s):

Vlsi Design ◽

Layout Problem ◽

Hybrid Heuristic ◽

Gate Matrix

Simulated annealing for target-oriented partial scan

Proceedings of 7th International Conference on VLSI Design ◽

10.1109/icvd.1994.282666 ◽

2002 ◽

Cited By ~ 3

Author(s):

C.P. Ravikumar ◽

H. Rasheed

Keyword(s):

Simulated Annealing ◽

Partial Scan

Flipping modules to improve circuit performance and routability

Proceedings of 7th International Conference on VLSI Design ◽

10.1109/icvd.1994.282670 ◽

2002 ◽

Author(s):

K. Ahn ◽

S. Sahni

Keyword(s):

Circuit Performance

A linear systolic array for LU decomposition

Proceedings of 7th International Conference on VLSI Design ◽

10.1109/icvd.1994.282718 ◽

2002 ◽

Cited By ~ 4

Author(s):

E. Casseau ◽

D. Degrugillier

Keyword(s):

Systolic Array ◽

Lu Decomposition

Synthesis of low power linear DSP circuits using activity metrics

Proceedings of 7th International Conference on VLSI Design ◽

10.1109/icvd.1994.282699 ◽

2002 ◽

Cited By ~ 35

Author(s):

A. Chatterjee ◽

R.K. Roy

Keyword(s):

Low Power

Proceedings of 7th International Conference on VLSI DesignLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Data path testability evaluation via functional testability measures

A 2K×1K space switch ASIC for use in digital exchanges

A methodology for architecture synthesis of cascaded IIR filters on TLU FPGAs

An optimal design for parallel test generation based on circuit partitioning

An empirical study on the effects of physical design in high-level synthesis

An efficient hybrid heuristic for the gate matrix layout problem in VLSI design

Simulated annealing for target-oriented partial scan

Flipping modules to improve circuit performance and routability

A linear systolic array for LU decomposition

Synthesis of low power linear DSP circuits using activity metrics

Proceedings of 7th International Conference on VLSI Design
Latest Publications