An optimal design for parallel test generation based on circuit partitioning

Proceedings of 7th International Conference on VLSI Design ◽

10.1109/icvd.1994.282706 ◽

2002 ◽

Author(s):

Dong Xiang ◽

Dao-Zheng Wei

Keyword(s):

Optimal Design ◽

Test Generation ◽

Circuit Partitioning ◽

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Parallel test generation using circuit partitioning and spectral techniques

Proceedings of the Sixth Euromicro Workshop on Parallel and Distributed Processing - PDP '98 - ◽

10.1109/empdp.1998.647208 ◽

2002 ◽

Author(s):

C. Gil ◽

J. Ortega

Keyword(s):

Test Generation ◽

Circuit Partitioning ◽

Spectral Techniques ◽

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Annealing-based heuristics and genetic algorithms for circuit partitioning in parallel test generation

Future Generation Computer Systems ◽

10.1016/s0167-739x(98)00045-4 ◽

1998 ◽

Vol 14 (5-6) ◽

pp. 439-451 ◽

Author(s):

C. Gil ◽

J. Ortega ◽

A.F. Díaz ◽

M.D.G. Montoya

Keyword(s):

Genetic Algorithms ◽

Test Generation ◽

Circuit Partitioning ◽

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Meta-heuristics for circuit partitioning in parallel test generation

Lecture Notes in Computer Science - Parallel and Distributed Processing ◽

10.1007/3-540-64359-1_702 ◽

1998 ◽

pp. 315-323 ◽

Author(s):

C. Gil ◽

J. Ortega ◽

A. F. Diaz ◽

M. G. Montoya

Keyword(s):

Test Generation ◽

Circuit Partitioning ◽

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An investigation of circuit partitioning for parallel test generation

Digest of Papers. 1992 IEEE VLSI Test Symposium ◽

10.1109/vtest.1992.232735 ◽

2003 ◽

Author(s):

S.W. Bollinger ◽

S.F. Midkiff

Keyword(s):

Test Generation ◽

Circuit Partitioning ◽

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Parallel test pattern generation using circuit partitioning in a shared-memory multiprocessor

Lecture Notes in Computer Science - Applied Parallel Computing Large Scale Scientific and Industrial Problems ◽

10.1007/bfb0095334 ◽

1998 ◽

pp. 167-171 ◽

Author(s):

Consolación Gil ◽

Julio Ortega ◽

Jose Luis Bernier ◽

Maria Dolores Gil

Keyword(s):

Shared Memory ◽

Test Pattern ◽

Pattern Generation ◽

Test Pattern Generation ◽

Circuit Partitioning ◽

Parallel Test ◽

Shared Memory Multiprocessor

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Using high-level primitives to speed up circuit partitioning in a mixed scan and non-scan environment for system level test generation

[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design ◽

10.1109/isvd.1991.185103 ◽

1991 ◽

Author(s):

S. Kode

Keyword(s):

Test Generation ◽

System Level ◽

Circuit Partitioning ◽

Speed Up ◽

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Portable parallel test generation for sequential circuits

IEEE/ACM International Conference on Computer-Aided Design ◽

10.1109/iccad.1992.279371 ◽

1992 ◽

Author(s):

Ramkumar ◽

Banerjee

Keyword(s):

Test Generation ◽

Sequential Circuits ◽

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Performance trade-offs in a parallel test generation/fault simulation environment

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.103504 ◽

1991 ◽

Vol 10 (12) ◽

pp. 1542-1558 ◽

Author(s):

S. Patil ◽

P. Banerjee

Keyword(s):

Test Generation ◽

Fault Simulation ◽

Simulation Environment ◽

Parallel Test ◽

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Workstation based parallel test generation

Proceedings of IEEE International Test Conference - (ITC) ◽

10.1109/test.1993.470670 ◽

2002 ◽

Author(s):

R.H. Klenke ◽

L. Kaufman ◽

J.H. Aylor ◽

R. Waxman ◽

P. Narayan

Keyword(s):

Test Generation ◽

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Parallel test generation for sequential circuits on general-purpose multiprocessors

Proceedings of the 28th conference on ACM/IEEE design automation conference - DAC '91 ◽

10.1145/127601.127651 ◽

1991 ◽

Author(s):

Srinivas Patil ◽

Prithviraj Banerjee ◽

Janak H. Patel

Keyword(s):

Test Generation ◽

General Purpose ◽

Sequential Circuits ◽

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