Proceedings Fifth International Symposium on High-Performance Computer Architecture
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Switch cache: a framework for improving the remote memory access latency of CC-NUMA multiprocessors

Proceedings Fifth International Symposium on High-Performance Computer Architecture ◽

10.1109/hpca.1999.744357 ◽

1999 ◽

Cited By ~ 12

Author(s):

R. Iyer ◽

L.N. Bhuyan

Keyword(s):

Memory Access ◽

Remote Memory ◽

Access Latency ◽

Remote Memory Access

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MMR: a high-performance MultiMedia Router-architecture and design trade-offs

Proceedings Fifth International Symposium on High-Performance Computer Architecture ◽

10.1109/hpca.1999.744383 ◽

1999 ◽

Cited By ~ 45

Author(s):

J. Duato ◽

S. Yalamanchili ◽

M.B. Caminero ◽

D. Love ◽

F.J. Quiles

Keyword(s):

High Performance ◽

Router Architecture ◽

Trade Offs ◽

Architecture And Design

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Impact of buffer size on the efficiency of deadlock detection

Proceedings Fifth International Symposium on High-Performance Computer Architecture ◽

10.1109/hpca.1999.744385 ◽

1999 ◽

Cited By ~ 2

Author(s):

J.M. Martinez ◽

P. Lopez ◽

J. Duato

Keyword(s):

Buffer Size ◽

Deadlock Detection

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LAPSES: a recipe for high performance adaptive router design

Proceedings Fifth International Symposium on High-Performance Computer Architecture ◽

10.1109/hpca.1999.744375 ◽

1999 ◽

Cited By ~ 14

Author(s):

A.S. Vaidya ◽

A. Sivasubramaniam ◽

C.R. Das

Keyword(s):

High Performance

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Limits to the performance of software shared memory: a layered approach

Proceedings Fifth International Symposium on High-Performance Computer Architecture ◽

10.1109/hpca.1999.744363 ◽

1999 ◽

Cited By ~ 1

Author(s):

A. Bilas ◽

Dongming Jiang ◽

Yuanyuan Zhou ◽

J.P. Singh

Keyword(s):

Shared Memory ◽

Layered Approach

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Distributed modulo scheduling

Proceedings Fifth International Symposium on High-Performance Computer Architecture ◽

10.1109/hpca.1999.744349 ◽

1999 ◽

Cited By ~ 23

Author(s):

M.M. Fernandes ◽

J. Llosa ◽

N. Topham

Keyword(s):

Modulo Scheduling

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A performance comparison of homeless and home-based lazy release consistency protocols in software shared memory

Proceedings Fifth International Symposium on High-Performance Computer Architecture ◽

10.1109/hpca.1999.744380 ◽

1999 ◽

Cited By ~ 10

Author(s):

A.L. Cox ◽

E. de Lara ◽

C. Hu ◽

W. Zwaenepoel

Keyword(s):

Shared Memory ◽

Performance Comparison ◽

Home Based ◽

Release Consistency ◽

A Performance

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Impulse: building a smarter memory controller

Proceedings Fifth International Symposium on High-Performance Computer Architecture ◽

10.1109/hpca.1999.744334 ◽

1999 ◽

Cited By ~ 85

Author(s):

J. Carter ◽

W. Hsieh ◽

L. Stoller ◽

M. Swanson ◽

Lixin Zhang ◽

...

Keyword(s):

Memory Controller

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The impact of link arbitration on switch performance

Proceedings Fifth International Symposium on High-Performance Computer Architecture ◽

10.1109/hpca.1999.744368 ◽

1999 ◽

Cited By ~ 11

Author(s):

M. Pirvu ◽

L. Bhuyan ◽

N. Ni

Keyword(s):

Switch Performance ◽

The Impact

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Instruction pre-processing in trace processors

Proceedings Fifth International Symposium on High-Performance Computer Architecture ◽

10.1109/hpca.1999.744347 ◽

1999 ◽

Cited By ~ 22

Author(s):

Q. Jacobson ◽

J.E. Smith

Keyword(s):

Trace Processors

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Proceedings Fifth International Symposium on High-Performance Computer ArchitectureLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Switch cache: a framework for improving the remote memory access latency of CC-NUMA multiprocessors

MMR: a high-performance MultiMedia Router-architecture and design trade-offs

Impact of buffer size on the efficiency of deadlock detection

LAPSES: a recipe for high performance adaptive router design

Limits to the performance of software shared memory: a layered approach

Distributed modulo scheduling

A performance comparison of homeless and home-based lazy release consistency protocols in software shared memory

Impulse: building a smarter memory controller

The impact of link arbitration on switch performance

Instruction pre-processing in trace processors

Proceedings Fifth International Symposium on High-Performance Computer Architecture
Latest Publications