Proceedings International Test Conference 1992
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TOTAL DOCUMENTS

131

(FIVE YEARS 0)

H-INDEX

19

(FIVE YEARS 0)

Published By IEEE

0780307607

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

I/sub DDQ/ TESTING IN CMOS DIGITAL ASIC'S - PUTTING IT ALL TOGETHER

Proceedings International Test Conference 1992 ◽

10.1109/test.1992.527815 ◽

2005 ◽

Author(s):

R. Perry

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ACCORD : Automatic Catching and Correction of Logic Design Errors in Combinational Circuits

Proceedings International Test Conference 1992 ◽

10.1109/test.1992.527896 ◽

2005 ◽

Author(s):

Pi-Yu Chung ◽

I.N. Hajj

Keyword(s):

Logic Design ◽

Combinational Circuits

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CCD IMAGE SENSOR TEST USING CELLULAR AUTOMATON-TYPE PATTERN RECOGNITION SYSTEM

Proceedings International Test Conference 1992 ◽

10.1109/test.1992.527825 ◽

2005 ◽

Author(s):

H. Kato

Keyword(s):

Pattern Recognition ◽

Cellular Automaton ◽

Recognition System ◽

Image Sensor ◽

Pattern Recognition System ◽

Ccd Image Sensor ◽

Type Pattern ◽

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ENHANCED PROBE CARD FACILITATES AT-SPEED WAFER PROBING IN VERY HIGH DENSITY APPLICATIONS

Proceedings International Test Conference 1992 ◽

10.1109/test.1992.527920 ◽

2005 ◽

Author(s):

E. Subramanian ◽

R. Nelson

Keyword(s):

High Density ◽

Wafer Probing ◽

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Simulation Of an Integrated Design and Test Environment For Mixed Signal Integrated Circuits

Proceedings International Test Conference 1992 ◽

10.1109/test.1992.527850 ◽

2005 ◽

Author(s):

S.C. Bateman ◽

W.H. Kao

Keyword(s):

Integrated Circuits ◽

Integrated Design ◽

Test Environment ◽

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Optimized BIST Strategies for Programmable Data Paths Based on Cellular Automata

Proceedings International Test Conference 1992 ◽

10.1109/test.1992.527811 ◽

2005 ◽

Author(s):

J. vanSas ◽

F. Catthoor ◽

H. DeMan

Keyword(s):

Cellular Automata

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Sequential circuit diagnosis based on formal verification techniques

Proceedings International Test Conference 1992 ◽

10.1109/test.1992.527819 ◽

2005 ◽

Author(s):

G. Cabodi ◽

P. Camurati ◽

F. Corno ◽

P. Prinetto ◽

M.S. Reorda

Keyword(s):

Formal Verification ◽

Sequential Circuit ◽

Verification Techniques

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Parity-Scan Design to Reduce the Cost of Test Application

Proceedings International Test Conference 1992 ◽

10.1109/test.1992.527835 ◽

2005 ◽

Author(s):

H. Fujiwara ◽

A. Yamamoto

Keyword(s):

Scan Design ◽

Test Application ◽

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A STEADY-STATE RESPONSE TEST GENERATION FOR MIXED-SIGNAL INTEGRATED CIRCUITS

Proceedings International Test Conference 1992 ◽

10.1109/test.1992.527851 ◽

2005 ◽

Author(s):

A.F. Alani ◽

G. Musgrave ◽

A.P. Ambler

Keyword(s):

Steady State ◽

Integrated Circuits ◽

Test Generation ◽

Steady State Response ◽

Mixed Signal ◽

Response Test ◽

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Detection of undetectable faults using IDDQ testing

Proceedings International Test Conference 1992 ◽

10.1109/test.1992.527899 ◽

2005 ◽

Author(s):

R.K. Gulati ◽

Weiwei Mao ◽

D.K. Goel

Keyword(s):

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