5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era
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70

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5

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Published By IEEE

9781424463381

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Statistical modeling for dysphonic classification

5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era ◽

10.1109/dtis.2010.5487588 ◽

2010 ◽

Author(s):

Assia Ghelis ◽

Mhania Guerti ◽

Corinne Fredouille

Keyword(s):

Statistical Modeling

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An analytical subthreshold swing model to study the scalability limits of double-gate MOSFETs including bulk traps effects

5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era ◽

10.1109/dtis.2010.5487568 ◽

2010 ◽

Author(s):

M.A. Abdi ◽

F. Djeffal ◽

D. Arar ◽

T. Bendib

Keyword(s):

Subthreshold Swing ◽

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A new PSO-based approach to study the nanoscale DG MOSFETs

5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era ◽

10.1109/dtis.2010.5487571 ◽

2010 ◽

Author(s):

T. Bendib ◽

F. Djeffal ◽

M. A. Abdi

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Verification of SystemC transaction level models using an aspect-oriented and generic approach

5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era ◽

10.1109/dtis.2010.5487605 ◽

2010 ◽

Author(s):

Meriam Kallel ◽

Younes Lahbib ◽

Rached Tourki ◽

Adel Baganne

Keyword(s):

Transaction Level

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A new built-in self-test (BIST) for a RF low-noise amplifier (LNA)

5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era ◽

10.1109/dtis.2010.5487559 ◽

2010 ◽

Author(s):

R. Ayadi ◽

M. Masmoudi

Keyword(s):

Low Noise ◽

Low Noise Amplifier ◽

Self Test ◽

Built In Self Test ◽

Noise Amplifier

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Design and FPGA implementation of modular multiplication methods using cellular automata

5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era ◽

10.1109/dtis.2010.5487586 ◽

2010 ◽

Author(s):

Z. Guitouni ◽

R. Chotin-Avot ◽

M. Machhout ◽

H. Mehrez ◽

R. Tourki

Keyword(s):

Cellular Automata ◽

Fpga Implementation ◽

Modular Multiplication

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Temperature and supply voltage aware power modeling of analog functions at system level

5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era ◽

10.1109/dtis.2010.5487601 ◽

2010 ◽

Author(s):

A. Suissa ◽

O. Romain ◽

J. Denoulet ◽

K. Hachicha ◽

P. Garda

Keyword(s):

Supply Voltage ◽

System Level ◽

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A new geometric approach to mobile position in wireless LAN reducing complex computations

5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era ◽

10.1109/dtis.2010.5487566 ◽

2010 ◽

Author(s):

Monji Zaidi ◽

Rached Tourki ◽

Ridha Ouni

Keyword(s):

Wireless Lan ◽

Geometric Approach

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Trends and challenges of SRAM reliability in the nano-scale era

5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era ◽

10.1109/dtis.2010.5487565 ◽

2010 ◽

Author(s):

Seyab Khan ◽

Said Hamdioui

Keyword(s):

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A concurrent BIST architecture based on Monitoring Square Windows

5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era ◽

10.1109/dtis.2010.5487561 ◽

2010 ◽

Author(s):

I. Voyiatzis ◽

Th. Haniotakis ◽

C. Efstathiou ◽

H. Antonopoulou

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