Analysis of Subthreshold Swing of Symmetric Junctionless Double Gate MOSFET Using Gaussian Doping Profile

—The variation of subthreshold swing(SS) according to the projected range (Rp ) and standard projected deviation (σp ) was analyzed when the symmetrical junctionless double gate (JLDG) MOSFET was doped with Gaussian doping profile. For this purpose, the analytical SS model was presented. We compared with the TCAD results to turn out the validity of this model, and the SSs of this model agreed with those of TCAD. The effective conduction path and mean doping concentration affecting the SS were analyzed according to the Rp and σp . As a result, the SS increased as the Rp and σp increased simultaneously. The smaller the Rp and the larger the σp , the lower the SS. When Rp = 1.5 nm, it showed the SS below 100mV/dec without being affected by the change of σp or silicon thickness. When σp = 3nm, it was also 100mV/dec or less regardless of the change of Rp and silicon thickness. Keywords— Double gate, Junctionless, Subthreshold swing, Gaussian, Projected range, Standard projected deviation

Positive-to-negative subthreshold swing of a MOSFET tuned by the ferroelectric switching dynamics of BiFeO3

Ferroelectricity can reduce the subthreshold swing (SS) of metal-oxide-semiconductor field-effect transistors (MOSFETs) to below the room-temperature Boltzmann limit of ~60 mV/dec and provides an important strategy to achieve a steeper SS. Surprisingly, by carefully tuning the polarization switching dynamics of BiFeO3 ferroelectric capacitors the SS of a commercial power MOSFET can even be tuned to zero or a negative value, i.e., the drain current increases with a constant or decreasing gate voltage. In particular, in addition to the positive SS of lower than 60 mV/dec, the zero and negative SS can be established with a drain current spanning for over seven orders of magnitude. These intriguing phenomena are explained by the ferroelectric polarization switching dynamics, which change the charge redistributions and accordingly affect the voltage drops across the ferroelectric capacitor and MOSFET. This study provides deep insights into understanding the steep SS in ferroelectric MOSFETs, which could be promising for designing advanced MOSFETs with an ultralow and tunable SS.

Steep Subthreshold Swing and Enhanced Illumination Stability InGaZnO Thin-Film Transistor by Plasma Oxidation on Silicon Nitride Gate Dielectric

In this paper, an InGaZnO thin-film transistor (TFT) based on plasma oxidation of silicon nitride (SiNx) gate dielectric with small subthreshold swing (SS) and enhanced stability under negative bias illumination stress (NBIS) have been investigated in detail. The mechanism of the high-performance InGaZnO TFT with plasma-oxidized SiNx gate dielectric was also explored. The X-ray photoelectron spectroscopy (XPS) results confirmed that an oxygen-rich layer formed on the surface of the SiNx layer and the amount of oxygen vacancy near the interface between SiNx and InGaZnO layer was suppressed via pre-implanted oxygen on SiNx gate dielectric before deposition of the InGaZnO channel layer. Moreover, the conductance method was employed to directly extract the density of the interface trap (Dit) in InGaZnO TFT to verify the reduction in oxygen vacancy after plasma oxidation. The proposed InGaZnO TFT with plasma oxidation exhibited a field-effect mobility of 16.46 cm2/V·s, threshold voltage (Vth) of −0.10 V, Ion/Ioff over 108, SS of 97 mV/decade, and Vth shift of −0.37 V after NBIS. The plasma oxidation on SiNx gate dielectric provides a novel approach for suppressing the interface trap for high-performance InGaZnO TFT.

Junctionless Gate-All-Around Nanowire FET with Asymmetric Spacer for Continued Scaling

In this paper we have performed scaling performance of asymmetric junctionless (JL) SOI nanowire FET at 10 nm gate length (LG). To study the device electrical performance various DC metrics like SS, DIBL, ION/IOFF ratio are performed. Even at 5 nm, the device has good electrical properties with subthreshold swing (SS) = 64 mV/dec, drain induced barrier lowering (DIBL) = 45 mV/V, and switching ratio (ION/IOFF) = 106 shows a higher level of electrostatic integrity. Moreover, to study scaling flexibility towards analog/RF applications various parameters like transconductance (I), transconductance generation factor (TGF), total gate capacitance (Cgg), and cutoff frequency (fT) are determined. Furthermore, the dynamic power (DP) and static power (SP) consumption of the device with scaling is also presented. The findings of the study show that asymmetric JL nanowire FET is one of the scaling possibilities.