[1991] Proceedings. First Great Lakes Symposium on VLSI
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TOTAL DOCUMENTS

(FIVE YEARS 0)

H-INDEX

(FIVE YEARS 0)

Published By IEEE Comput. Soc. Press

0818621702

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Gate level representation of ECL circuits for fault modeling

[1991] Proceedings. First Great Lakes Symposium on VLSI ◽

10.1109/glsv.1991.143989 ◽

2002 ◽

Cited By ~ 5

Author(s):

S.M. Menon ◽

A.P. Jayasumana ◽

Y.K. Malaiya

Keyword(s):

Fault Modeling

Implementation of fault-tolerant sequential circuits using programmable logic arrays

[1991] Proceedings. First Great Lakes Symposium on VLSI ◽

10.1109/glsv.1991.143954 ◽

2002 ◽

Author(s):

N. Misra ◽

A.K. Goel

Keyword(s):

Fault Tolerant ◽

Sequential Circuits ◽

Programmable Logic ◽

Programmable Logic Arrays

GALSY, an automatic layout generator of symbolic layouts from MOS circuit schematics

[1991] Proceedings. First Great Lakes Symposium on VLSI ◽

10.1109/glsv.1991.143982 ◽

2002 ◽

Author(s):

N. Baha ◽

M. Beddiaf ◽

A.-K. Gadiri

Keyword(s):

Automatic Layout

A test controller board for TSS

[1991] Proceedings. First Great Lakes Symposium on VLSI ◽

10.1109/glsv.1991.143939 ◽

2002 ◽

Cited By ~ 2

Author(s):

K.T. Kornegay ◽

R.W. Brodersen

Keyword(s):

Controller Board

A CAD tool for designing large, fault-tolerant VLSI arrays

[1991] Proceedings. First Great Lakes Symposium on VLSI ◽

10.1109/glsv.1991.143955 ◽

2002 ◽

Cited By ~ 1

Author(s):

P. Poechmueller ◽

G.K. Sharma ◽

M. Glesner

Keyword(s):

Fault Tolerant ◽

Cad Tool

Four layer wiring using adjacent-layer vias

[1991] Proceedings. First Great Lakes Symposium on VLSI ◽

10.1109/glsv.1991.143960 ◽

2002 ◽

Author(s):

T.K. Wu ◽

M.L. Brady

Keyword(s):

Adjacent Layer

Discrete Fourier transform processors using CORDIC

[1991] Proceedings. First Great Lakes Symposium on VLSI ◽

10.1109/glsv.1991.143976 ◽

2002 ◽

Cited By ~ 1

Author(s):

Jeong-A Lee ◽

Kiseon Kim

Keyword(s):

Fourier Transform ◽

Discrete Fourier Transform

Test plan generation and concurrent scheduling of tests in the presence of conflicts

[1991] Proceedings. First Great Lakes Symposium on VLSI ◽

10.1109/glsv.1991.143973 ◽

2002 ◽

Author(s):

T.C. Wilson ◽

A. Basu ◽

D.K. Banerji ◽

J.C. Majithia

Keyword(s):

Test Plan ◽

Plan Generation ◽

Concurrent Scheduling ◽

Test Plan Generation

A new approach to timing driven partitioning of combinational logic

[1991] Proceedings. First Great Lakes Symposium on VLSI ◽

10.1109/glsv.1991.143949 ◽

2002 ◽

Cited By ~ 1

Author(s):

N. Wehn ◽

M. Glesner

Keyword(s):

Combinational Logic ◽

New Approach

A hierarchical multi-level test generation system

[1991] Proceedings. First Great Lakes Symposium on VLSI ◽

10.1109/glsv.1991.143942 ◽

2002 ◽

Author(s):

A. Lioy ◽

M. Poncino

Keyword(s):

Test Generation ◽

Generation System ◽

Multi Level

[1991] Proceedings. First Great Lakes Symposium on VLSILatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE Comput. Soc. Press

Gate level representation of ECL circuits for fault modeling

Implementation of fault-tolerant sequential circuits using programmable logic arrays

GALSY, an automatic layout generator of symbolic layouts from MOS circuit schematics

A test controller board for TSS

A CAD tool for designing large, fault-tolerant VLSI arrays

Four layer wiring using adjacent-layer vias

Discrete Fourier transform processors using CORDIC

Test plan generation and concurrent scheduling of tests in the presence of conflicts

A new approach to timing driven partitioning of combinational logic

A hierarchical multi-level test generation system

[1991] Proceedings. First Great Lakes Symposium on VLSI
Latest Publications