System on Chip Design Languages
Latest Publications

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24

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2

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Published By Springer US

9781441952813, 9781475766745

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

VHDL-AMS Model of a Synchronous Oscillator including Phase Noise

System on Chip Design Languages ◽

10.1007/978-1-4757-6674-5_4 ◽

2002 ◽

pp. 45-58 ◽

Author(s):

A. Fakhfakh ◽

N. Milet-Lewis ◽

J-B. Bégueret ◽

H. Lévi

Keyword(s):

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Advanced ASIC Sign-Off Features of IEEE 1076.4-2000 And Standards updates to Verilog and SDF

System on Chip Design Languages ◽

10.1007/978-1-4757-6674-5_3 ◽

2002 ◽

pp. 35-42

Author(s):

Steve Wadsworth ◽

Dennis Brophy

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Aspects Of Object Oriented Hardware Modelling With SystemC-Plus

System on Chip Design Languages ◽

10.1007/978-1-4757-6674-5_18 ◽

2002 ◽

pp. 213-223 ◽

Author(s):

Eike Grimpe ◽

Frank Oppenheimer

Keyword(s):

Object Oriented

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A Mixed C/Verilog Dual-Platform Simulator

System on Chip Design Languages ◽

10.1007/978-1-4757-6674-5_15 ◽

2002 ◽

pp. 175-186

Author(s):

David A. Burgoon ◽

Edward W. Powell ◽

John A. Sundragon Waitz

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The Guidelines and JPEG Encoder Study Case of System Level Architecture Exploration Using the SpecC Methodology

System on Chip Design Languages ◽

10.1007/978-1-4757-6674-5_13 ◽

2002 ◽

pp. 151-161 ◽

Author(s):

Lukai Cai ◽

Mike Olivarez ◽

Dan Gajski

Keyword(s):

System Level ◽

Architecture Exploration ◽

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Wild Blue Yonder: Experiences in Designing an FPGA with State Machines for a Modern Fighter Jet, Using VHDL and DesignBook

System on Chip Design Languages ◽

10.1007/978-1-4757-6674-5_11 ◽

2002 ◽

pp. 129-137

Author(s):

Brian L. Snyder

Keyword(s):

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VHDL 2001: What’s New

System on Chip Design Languages ◽

10.1007/978-1-4757-6674-5_1 ◽

2002 ◽

pp. 3-10

Author(s):

J. Bhasker ◽

Paul J. Menchini

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Analog Filter Synthesis from VHDL-AMS

System on Chip Design Languages ◽

10.1007/978-1-4757-6674-5_9 ◽

2002 ◽

pp. 99-109

Author(s):

Fazrena A. Hamid ◽

Tom J. Kazmierski

Keyword(s):

Analog Filter ◽

Filter Synthesis

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A unified IP Design Platform for extremly flexible High Performance RF and AMS Macros using Standard Design Tools

System on Chip Design Languages ◽

10.1007/978-1-4757-6674-5_8 ◽

2002 ◽

pp. 87-97 ◽

Author(s):

Reimund Wittmann ◽

Mohsen Darianian ◽

Dirk Bierbaum ◽

Pasi Ruhanen ◽

Werner Schardein

Keyword(s):

High Performance ◽

Design Tools ◽

Standard Design

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A System Benchmark Specification Experiment with Esterel/C

System on Chip Design Languages ◽

10.1007/978-1-4757-6674-5_21 ◽

2002 ◽

pp. 247-253

Author(s):

Lluíds Ribas ◽

Joaquín Saiz ◽

Jordi Carrabina

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