The Guidelines and JPEG Encoder Study Case of System Level Architecture Exploration Using the SpecC Methodology

System on Chip Design Languages ◽

10.1007/978-1-4757-6674-5_13 ◽

2002 ◽

pp. 151-161 ◽

Author(s):

Lukai Cai ◽

Mike Olivarez ◽

Dan Gajski

Keyword(s):

System Level ◽

Architecture Exploration ◽

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System-Level Specification and Architecture Exploration : an Avionics Codesign Application

Electronic Chips & Systems Design Languages ◽

10.1007/978-1-4757-3326-6_9 ◽

2001 ◽

pp. 111-120

Author(s):

François Cloute ◽

Jean-Noël Contensou ◽

Daniel Esteve ◽

Pascal Pampagnin ◽

Philippe Pons ◽

...

Keyword(s):

System Level ◽

Architecture Exploration

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System-Level Bus-Based Communication Architecture Exploration Using a Pseudoparallel Algorithm

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2009.2021733 ◽

2009 ◽

Vol 28 (8) ◽

pp. 1213-1223 ◽

Author(s):

Lih-Yih Chiou ◽

Yi-Siou Chen ◽

Chih-Hsien Lee

Keyword(s):

System Level ◽

Communication Architecture ◽

Architecture Exploration

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System-level memory modeling for bus-based memory architecture exploration

2009 IEEE International Conference on Electro/Information Technology ◽

10.1109/eit.2009.5189619 ◽

2009 ◽

Author(s):

Zhongbo Cao ◽

Ramon Mercado ◽

Diane T. Rover

Keyword(s):

System Level ◽

Memory Architecture ◽

Architecture Exploration ◽

Memory Modeling

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Interconnect-based system-level energy and power prediction to guide architecture exploration

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2004.825832 ◽

2004 ◽

Vol 12 (4) ◽

pp. 373-380 ◽

Author(s):

S.A. Wadekar ◽

A.C. Parker

Keyword(s):

System Level ◽

Level Energy ◽

Power Prediction ◽

Architecture Exploration

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System Level Architecture Exploration for Reconfigurable Systems On Chip

2006 International Conference on Field Programmable Logic and Applications ◽

10.1109/fpl.2006.311195 ◽

2006 ◽

Author(s):

Konstantinos Masselos ◽

Yang Qu ◽

Kari Tiensyrja ◽

Nikolaos Voros ◽

Miroslav Cupak ◽

...

Keyword(s):

System Level ◽

Reconfigurable Systems ◽

Architecture Exploration ◽

Systems On Chip ◽

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System-level interconnect architecture exploration for custom memory organizations

International Symposium on System Synthesis (IEEE Cat. No.01EX526) ◽

10.1145/500001.500005 ◽

2001 ◽

Author(s):

Tycho van Meeuwen ◽

Arnout Vandecappelle ◽

Allert van Zelst ◽

Francky Catthoor ◽

Diederik Verkest

Keyword(s):

System Level ◽

Architecture Exploration

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A Methodology for Architecture Exploration and Performance Analysis Using System Level Design Languages and Rapid Architecture Profiling

2008 International Symposium on Industrial Embedded Systems ◽

10.1109/sies.2008.4577686 ◽

2008 ◽

Author(s):

Alena Simalatsar ◽

Roberto Passerone ◽

Douglas Densmore

Keyword(s):

Performance Analysis ◽

System Level ◽

System Level Design ◽

Architecture Exploration ◽

Design Languages ◽

Level Design ◽

And Performance

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Introduction of system level architecture exploration using the SpecC methodology

ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196) ◽

10.1109/iscas.2001.921971 ◽

2002 ◽

Author(s):

L. Cai ◽

D. Gajski ◽

M. Olivarez

Keyword(s):

System Level ◽

Architecture Exploration

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System-level interconnect architecture exploration for custom memory organizations

International Symposium on System Synthesis (IEEE Cat. No.01EX526) ◽

10.1109/isss.2001.957906 ◽

2002 ◽

Author(s):

T. van Meeuwen ◽

A. Vandecappelle ◽

A. van Zelst ◽

F. Catthoor ◽

D. Verkest

Keyword(s):

System Level ◽

Architecture Exploration

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Session FB1 system level architecture exploration

2009 IEEE International SOC Conference (SOCC) ◽

10.1109/soccon.2009.5398011 ◽

2009 ◽

Keyword(s):

System Level ◽

Architecture Exploration

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