Optimal Reduction in the Number of Test Vectors for Soft Processor Cores Implemented in FPGA

Testing FPGA-based soft processor cores requires a completely different methodology in comparison to standard processors. The stuck-at fault model is insufficient, as the logic is implemented by lookup tables (LUTs) in FPGA, and this SRAM-based LUT memory is vulnerable to single-event upset (SEU) mainly caused by cosmic radiations. Consequently, in this paper, we used combined SEU-induced and stuck-at fault models to simulate every possible fault. The test program written in an assembler was based on the bijective property. Furthermore, the fault detection matrix was determined, and this matrix describes the detectability of every fault by every test vector. The major novelty of this paper is the optimal reduction in the number of required test vectors in such a way that fault coverage is not reduced. Furthermore, this paper also studied the optimal selection of test vectors when only 95% maximal fault coverage is acceptable; in such a case, only three test vectors are required. Further, local and global test vector selection is also described.

Analisis Algoritma SHA-3 Keamanan pada Data Pribadi

Data Pribadi merupakan data yang harus dilindungi di era yang serba internet ini. Karena data tersebut berisi informasi penting yang bisa saja menjadi sasaran cyber crime.Beberapa tahun terakhir marak terjadi kasus penyerangan atau hacking yang mengambil data dan digunakan tidak semestinya oleh orang yang tidak bertanggung jawab. Dalam penelitian ini bertujuan untuk merancang sistem keamanan untuk mengamankan data tersebut.Salah satu algoritma yang dapat digunakan adalah algoritma SHA-3 untuk menjamin kerahasiaan dan keutuhan data.Pengujian yang dilakukan pada penelitian ini adalah validasi enkripsi dan dekripsi, waktu enkripsi dan dekripsi, fungsionalitas sistem dan non fungsionalitas sistem. Hasil pengujian pada penelitian ini menghasilkan, Pengujian test vector: Test Vector algoritme SHA-3, Pengujian performance Waktu, Pengujian waktu enkripsi data kosong, Pengujian waktu enkripsi data 1-char, Pengujian waktu enkripsi data fullchar, Pengujian waktu dekripsi data kosong, Pengujian waktu dekripsi data 1-char, Pengujian waktu dekripsi data fullchar, Pengujian validasi enkripsi dan dekripsi dan Pengujian Fungsional dan Nonfungsional. Kata kunci: SHA-3, Enkripsi, Dekripsi

Adjustable PRPG for Low Power Test Patterns

As the power consumption is more in the processes of testing, test vector set compression and controlling of toggling plays a crucial role in reducing the power consumption during test mode. In exploring the controlling techniques of toggling, Pre-Selected Toggling (PRESTO) of test patterns is a technique that can control the toggling of a test patterns in a precise manner in Built-in Self -Test (BIST) architectures. In this paper we modify the architecture of existing Full Version PRESTO that can be used to generate test vectors and in addition binary sequences used as scan chins such that the controlling of sequence of test vectors depends on number of 1’s present in the switch code which is user defined thus reducing the testing time with significant fault coverage, and in addition the optimization is also observed in area and power. The area has decreased by 12.2% and power consumption by 15.43%. The Synthesis and implementation of the architectures are done using Artix7 (xc7a100tcsg324-3) FPGA family. The simulation results have been analyzed through Mentor-graphics Questa-sim 10.7C

Application of PODEM Algorithm for Fault Detection and Location in FinFet based Combinational VLSI Circuits

FinFet transistors are used in major semiconductor organizations and a significant role is played by it in developing the silicon industries. Due to few embedded memories and other circuit issues the transistors have specific faults in manufacturing, designing of the circuit etc. This paper presents an advanced test algorithm to diagnose those faults. The circuit with different gates is designed to identify the places having faults. In addition, different algorithms such as PODEM (Path Oriented Decision Making algorithms) are used to find the fault detection and location. The Furthermore, more complicated circuits are analyzed for fault detection with different approach. In this research work Combinational Circuits are designed using 20nm/32nm technology nodes in LT Spice environment and PODEM Algorithm is implemented which is developed in MATLAB, to detect and identify fault location and sensitive test vector to detect fault in the circuit and results are presented..

Loop Transformation Algorithm for Test Vector Accessing at High Speed

Looping on test vectors is a widespread requirement in failure analysis of semiconductor devices. The start of the loop and the number of vectors in the loop can be of critical importance. Present-day vector memory architecture tends to impose restrictions on both due to test speed requirements. A new Vector Loop Transformation algorithm is introduced to remedy the tester constraints.