Test data compression and test time reduction of longest-path-per-gate tests based on Illinois scan architecture

Author(s):  
M. Sharma ◽  
J.H. Patel ◽  
J. Rearick
2010 ◽  
Vol 439-440 ◽  
pp. 1595-1600
Author(s):  
Chun Jian Deng ◽  
Liu Wei ◽  
Xi Feng Zheng ◽  
Liang Yang

Test data compression has been an effective way to reduce test data volume and test time, as well as to solve automatic test equipment (ATE) memory and bandwidth limitation. We analyze the limitations of current test data compression algorithm and draw on the previous experience to deduce an optimal compression coding model suitable for SoC test data. In addition, in this paper we make full use of the relevance of the test vectors and the advantages of statistical coding to present an efficient test data compression method RLE-G based on the coding model, and give the RLE-G the optimal compression efficiency of the boundary conditions and realization steps. The experimental results for ISCAS 89 benchmark circuits demonstrate RLE-G have the excellent advantages of high compression ratio.


2009 ◽  
Vol 31 (10) ◽  
pp. 1826-1834 ◽  
Author(s):  
Wen-Fa ZHAN ◽  
Hua-Guo LIANG ◽  
Feng SHI ◽  
Zheng-Feng HUANG

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