2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)
Latest Publications

TOTAL DOCUMENTS

132

(FIVE YEARS 0)

H-INDEX

(FIVE YEARS 0)

Published By IEEE

9784886860941, 9784886860965

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

ISPSD2017 Contributory Award [and two other awards]

2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD) ◽

10.23919/ispsd.2017.7988868 ◽

2017 ◽

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Author index ISPSD2017

2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD) ◽

10.23919/ispsd.2017.7988867 ◽

2017 ◽

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RFC diode with high avalanche stability and UIS capability

2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD) ◽

10.23919/ispsd.2017.7988944 ◽

2017 ◽

Cited By ~ 1

Author(s):

Fumihito Masuoka ◽

Koji Tanaka ◽

Takao Kachi ◽

Yasuhiro Yoshiura ◽

Kazuhiro Shimizu

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U-shaped channel SOI-LIGBT with dual trenches to improve the trade-off between saturation voltage and turn-off loss

2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD) ◽

10.23919/ispsd.2017.7988961 ◽

2017 ◽

Cited By ~ 2

Author(s):

Long Zhang ◽

Jing Zhu ◽

Weifeng Sun ◽

Minna Zhao ◽

Jiajun Chen ◽

...

Keyword(s):

Trade Off

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SiC MOSFET with built-in SBD for reduction of reverse recovery charge and switching loss in 10-kV applications

2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD) ◽

10.23919/ispsd.2017.7988890 ◽

2017 ◽

Cited By ~ 11

Author(s):

Huaping Jiang ◽

Jin Wei ◽

Xiaoping Dai ◽

Changwei Zheng ◽

Maolong Ke ◽

...

Keyword(s):

Switching Loss

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Process design of superjunction MOSFETs for high drain current capability and low on-resistance

2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD) ◽

10.23919/ispsd.2017.7988882 ◽

2017 ◽

Cited By ~ 1

Author(s):

Wataru Saito

Keyword(s):

Process Design ◽

Drain Current

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An advanced bimode insulated gate transistor BIGT with low diode conduction losses under a positive gate bias

2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD) ◽

10.23919/ispsd.2017.7988884 ◽

2017 ◽

Cited By ~ 1

Author(s):

Munaf Rahimo ◽

Charalampos Papadopoulos ◽

Chiara Corvasce ◽

Amost Kopta

Keyword(s):

Gate Bias

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High aspect ratio deep trench termination (HARDT2) technique surrounding die edge as dielectric wall to improve high voltage device area efficiency

2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD) ◽

10.23919/ispsd.2017.7988883 ◽

2017 ◽

Cited By ~ 2

Author(s):

Takuya Yamaguchi ◽

Hideki Okumura ◽

Tatsuya Shiraishi ◽

Tsuyoshi Fujita ◽

Yoshifumi Ata ◽

...

Keyword(s):

Aspect Ratio ◽

High Voltage ◽

High Aspect Ratio ◽

Deep Trench ◽

Dielectric Wall ◽

Area Efficiency

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Call for papers

2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD) ◽

10.23919/ispsd.2017.7988871 ◽

2017 ◽

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Relation between UIS withstanding capability and gate leakage currents for high voltage GaN-HEMTs

2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD) ◽

10.23919/ispsd.2017.7988922 ◽

2017 ◽

Cited By ~ 3

Author(s):

Toshiyuki Naka ◽

Wataru Saito

Keyword(s):

High Voltage ◽

Gate Leakage ◽

Leakage Currents ◽

Gan Hemts

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2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

ISPSD2017 Contributory Award [and two other awards]

Author index ISPSD2017

RFC diode with high avalanche stability and UIS capability

U-shaped channel SOI-LIGBT with dual trenches to improve the trade-off between saturation voltage and turn-off loss

SiC MOSFET with built-in SBD for reduction of reverse recovery charge and switching loss in 10-kV applications

Process design of superjunction MOSFETs for high drain current capability and low on-resistance

An advanced bimode insulated gate transistor BIGT with low diode conduction losses under a positive gate bias

High aspect ratio deep trench termination (HARDT2) technique surrounding die edge as dielectric wall to improve high voltage device area efficiency

Call for papers

Relation between UIS withstanding capability and gate leakage currents for high voltage GaN-HEMTs

2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)
Latest Publications