Impact of In Situ NH3 pre-treatment of LPCVD SiN passivation on GaN HEMT performance

The impact on the performance of GaN HEMTs of in situ ammonia (NH3) pre-treatment prior to the deposition of silicon nitride (SiN) passivation with low-pressure chemical vapor deposition is investigated. Three different NH3 pre-treatment durations (0, 3, and 10 minutes) were compared in terms of interface properties and device performance. A reduction of oxygen at the interface between SiN and epi-structure is detected by Scanning Transmission Electron Microscopy-Electron Energy Loss Spectroscopy measurements in the sample subjected to 10 minutes of pre-treatment. The samples subjected to NH3 pre-treatment show a reduced surface-related current dispersion of 9 % (compared to 16% for the untreated sample), which is attributed to the reduction of oxygen at the SiN/epi interface. Furthermore, NH3 pre-treatment for 10 minutes significantly improves the current dispersion uniformity from 14.5 % to 1.9 %. The reduced trapping effects result in a high output power of 3.4 W/mm at 3 GHz (compared to 2.6 W/mm for the untreated sample). These results demonstrate that the in situ NH3 pre-treatment before low-pressure chemical vapor deposition of SiN passivation is critical and can effectively improves the large-signal microwave performance of GaN HEMTs.

Scaling Behavior of InAlN/GaN HEMTs on Silicon for RF Applications

Due to the low cost and the scaling capability of Si substrate, InAlN/GaN high-electron-mobility transistors (HEMTs) on silicon substrate have attracted more and more attentions. In this paper, a high-performance 50-nm-gate-length InAlN/GaN HEMT on Si with a high on/off current (Ion/Ioff) ratio of 7.28 × 106, an average subthreshold swing (SS) of 72 mV/dec, a low drain-induced barrier lowing (DIBL) of 88 mV, an off-state three-terminal breakdown voltage (BVds) of 36 V, a current/power gain cutoff frequency (fT/fmax) of 140/215 GHz, and a Johnson’s figure-of-merit (JFOM) of 5.04 THz∙V is simultaneously demonstrated. The device extrinsic and intrinsic parameters are extracted using equivalent circuit model, which is verified by the good agreement between simulated and measured S-parameter values. Then the scaling behavior of InAlN/GaN HEMTs on Si is predicted using the extracted extrinsic and intrinsic parameters of devices with different gate lengths (Lg). It presents that a fT/fmax of 230/327 GHz can be achieved when Lg­ scales down to 20 nm with the technology developed in the study, and an improved fT/fmax of 320/535 GHz can be achieved on a 20-nm-gate-length InAlN/GaN HEMT with regrown ohmic contact technology and 30% decreased parasitic capacitance. This study confirms the feasibility of further improvement of InAlN/GaN HEMTs on Si for RF applications.

Scaling Behavior of Sub-100 nm InAlN/GaN HEMTs on Silicon for RF Applications

Due to the low cost and the scaling capability of Si substrate, InAlN/GaN high-electron-mobility transistors (HEMTs) on silicon substrate have attracted more and more attentions. In this paper, a high-performance 50-nm-gate-length InAlN/GaN HEMT on Si with a high on/off current (Ion/Ioff) ratio of 7.28 × 106, an average subthreshold swing (SS) of 72 mV/dec, a low drain-induced barrier lowing (DIBL) of 88 mV, an off-state three-terminal breakdown voltage (BVds) of 36 V, a current/power gain cutoff frequency (fT/fmax) of 140/215 GHz, and a Johnson’s figure-of-merit (JFOM) of 5.04 THz∙V is simultaneously demonstrated. The device extrinsic and intrinsic parameters are extracted using equivalent circuit model, which is verified by the good agreement between simulated and measured S-parameter values. Then the scaling behavior of InAlN/GaN HEMTs on Si is predicted using the extracted extrinsic and intrinsic parameters of devices with different gate lengths (Lg). It presents that a fT/fmax of 230/327 GHz can be achieved when Lg­ scales down to 20 nm with the technology developed in the study, and an improved fT/fmax of 320/535 GHz can be achieved on a 20-nm-gate-length InAlN/GaN HEMT with regrown ohmic contact technology and 30% decreased parasitic capacitance. This study confirms the feasibility of further improvement of InAlN/GaN HEMTs on Si for RF applications.

Design of Hybrid Schottky-Ohmic Gate in Normally-Off p-GaN Gate AlGaN/GaN HEMTs

This study proposes three hybrid Schottky-ohmic gate structures for normally-off p-GaN gate AlGaN/GaN HEMTs. One has a Schottky-gate cover on the ohmic-gate and has part of the area contact to the p-GaN surface at the left and right sides of ohmic-gate (Structure A). The two others only have the Schottky-gate contact to the p-GaN surface at the left side (Structure B) or right side (Structure C) of the ohmic-gate. Different gate metal designs change the hole injection from p-GaN to GaN channel and show various gate leakages. The optimized contact length of Schottky-gate can suppress on-state gate leakage current over two orders of magnitude compared to conventional ohmic p-GaN gate HEMT. The improved on-state maximum drain current is over 60 mA/mm compared to Schottky p-GaN gate HEMT. Optimal performance in Structure B with Schottky-gate contact length ranges from 0.8 to 1.8 μm in a 2 μm gate geometry.

Experimental and numerical investigation of Poole-Frenkel effect on dynamic R ON transients in C-doped p-GaN HEMTs

In this paper, we investigate the influence of Poole-Frenkel Effect (PFE) on the dynamic R ON transients in C-doped p-GaN HEMTs. To this aim, we perform a characterization of the dynamic R ON transients acquired during OFF-state stress (i.e., V GS,STR = 0 V < V T, V DS,STR = 25–125 V and we interpret the results with the aid of numerical simulations. We find that dynamic R ON transients at room temperature accelerate with V DS,STR 1/2, which is signature of PFE, as further confirmed by the simultaneous decrease of the activation energy (E A) extracted from the Arrhenius plot of the dynamic R ON transients at V DS,STR = 50 V and T = 30–110 °C. Results obtained by means of calibrated numerical simulations reproduce the exponential dependence of transients time constants (τ) on V DS,STR 1/2 and consequent E A reduction only when including PFE enhancement of hole emission from dominant acceptor traps in the buffer related to C doping. This result is consistent with the model that considers hole emission from acceptor traps (rather than electron capture) as the mechanism underlying dynamic R ON increase during OFF-state stress.

Normally-off GaN HEMTs with InGaN p-gate cap layer formed by polarization doping

Narrow gate margin has been the critical limiting factor for the p-gate normally-off GaN HEMTs, imposing significant challenges in both gate-drive design and gate reliability. In this work, by developing dopant-free p-type polarization doping technique in composition-graded InGaN layer, high-quality Schottky contact between the gate metal and cap layer was demonstrated, achieving excellent gate current blocking performance (10-6 mA/mm) after the turning-on of the gate heterojunction structure. Resultantly, normally-off GaN HEMTs with enhanced gate breakdown voltage up to 15.2 V was realized, being especially beneficial for the simplification of gate drive design and the safe operation of gate terminal.