Solar Powered Resonant Inverter Fed a High Voltage DC Power Supply

This paper proposes a solar-powered resonant inverter fed a high-voltage DC power supply. In this converter, switching loss is controlled through zero-voltage switching and zero-current switching. This converter comprises a solar panel, boost converter, full-bridge LLC resonant tank, power transformer, and rectifier circuit. All power switches are operated with an interleaved switching cycle to ensure equal power flow from the tank. This proposed converter is designed to produce a regulated 19.5 KV at output, with an input voltage range of 300–350 V. The proposed converter was simulated in PSpice to verify the results.

Performance Modelling and Design Techniques for Efficiency Improvement in On-chip Switched-Capacitor DC-DC Converter

Fundamental charge vector method analysis is a single parameter optimization technique limited to conduction loss assuming all frequency-dependent switching (parasitic) loss negligible. This paper investigates a generalized structure to design DC-DC SC converters based on conduction and switching loss. A new technique is proposed to find the optimum value of switching frequency and switch size to calculate target load current and output voltage that maximize the efficiency. The analysis is done to identify switching frequency and switch size for two-phase 2:1 series-parallel SC converter for a target load current of 2.67mA implemented on a 22nm technology node. Results show that a minimum of 250MHz switching frequency is required for target efficiency more than 90% and the output voltage greater than 0.85V where the switch size of a unit cell corresponds to 10Ω on-resistance. MATLAB and PSpice simulation tools are used for results and validation.

Constant-Current, Constant-Voltage Operation of a Dual-Bridge Resonant Converter: Modulation, Design and Experimental Results

To meet the requirements of charging the mainstream rechargeable batteries, in this work, a dual-bridge resonant converter (DBRC) is operated as a battery charger. Thanks to the features of this topology, the required high efficiency can be achieved with a wide range of battery voltage and current by using different modulation variables. Firstly, a typical charging process including constant-voltage stage and constant-current stage is indicated. Then, two different modulation methods of the DBRC are proposed, both of which can realize constant-voltage charging and constant-current charging. Method I adopts phase-shift modulation with constant switching frequency while Method II adopts varying frequency modulation. Furthermore, as guidance for practical application, the design principles and detailed design procedures of the DBRC are customized for the two modulation methods respectively in order to reduce the switching loss and conduction loss. Consequently, the full soft-switching operation with low rms tank current is achieved under the two modulation methods, which contributes to the high efficiency of the whole charging process. At last extensive simulation and experimental tests on a lab prototype converter are performed, which prove the feasibility and effectiveness of the proposed modulation strategies.

Improvement of Q rr-I DSS and dynamic avalanche of field-plate MOSFET by local lifetime control on the cathode side

Reducing the reverse recovery charge (Qrr) is effective for reducing switching loss in field plate (FP)-MOSFETs. A lifetime killer is utilized to reduce Qrr while increasing the leakage current in the off-state. Device simulation shows that a local lifetime killer on the cathode side successfully improves the trade-off between Qrr and IDSS in comparison with that of a uniform lifetime killer. A known issue of cathode lifetime killers is overshoot voltage by hard recovery. However, the overshoot voltage of FP-MOSFET decreases with a cathode lifetime killer owing to an internal snubber, which is a feature of FP-MOSFETs. An internal snubber with a large series resistance causes dynamic avalanche by both the increase of FP potential and excess carriers in high-speed operation. The cathode lifetime killer also improves dynamic avalanche by excess carriers. Consequently, the cathode lifetime killer is preferable for high-speed FP-MOSFETs.

A Carrier-Based Discontinuous PWM Strategy of NPC Three-Level Inverter for Common-Mode Voltage and Switching Loss Reduction

For the conventional carrier-based pulse width modulation (CBPWM) strategies of neutral point clamped (NPC) three-level inverters, the higher common-mode voltage (CMV) is a major drawback. However, with CMV suppression strategies, the switching loss is relatively high. In order to solve the above issue, a carrier-based discontinuous PWM (DPWM) strategy for NPC three-level inverter is proposed in this paper. Firstly, the reference voltage is modified by the twice injection of zero-sequence voltage. Switching states of the three-phase are clamped alternatively to reduce both the CMV and the switching loss. Secondly, the carriers are also modified by the phase opposite disposition of the upper and lower carriers. The extra switching at the border of two adjacent regions in the space vector diagram is reduced. Meanwhile, a neutral-point voltage (NPV) control method is also presented. The duty cycle of the switching state that affects the NPV is adjusted to obtain the balance control of the NPV. Still, the switching sequence in each carrier period remains the same. Finally, the feasibility and effectiveness of the proposed DPWM strategy are tested on a rapid control prototype platform based on RT-Lab.

Modulation Technique for Modified Active Quasi-Z-Source Inverter with Common-Mode Voltage Reduction

In Z-source topologies, a high-amplitude common-mode voltage can occur when shoot-through states are inserted. In this study, a new space vector pulse-width modulation for an active quasi-Z-source topology is proposed to operate at a high modulation index and reduce the common-mode voltage to one-third of the DC-link voltage. Moreover, the quality of the output voltage is improved by operation with a high modulation index and decreasing the switching loss of the H-bridge switches. The detailed operating principles of the active quasi-Z-source topology using the proposed space vector modulation (SVM) method are presented. A simulation model was built, and an experimental prototype was verified to correct the theoretical analysis.

A LysR-Type Transcriptional Regulator Controls Multiple Phenotypes in Acinetobacter baumannii

Acinetobacter baumannii is a multidrug-resistant, Gram-negative nosocomial pathogen that exhibits phenotypic heterogeneity resulting in virulent opaque (VIR-O) and avirulent translucent (AV-T) colony variants. Each variant has a distinct gene expression profile resulting in multiple phenotypic differences. Cells interconvert between the VIR-O and AV-T variants at high frequency under laboratory conditions, suggesting that the genetic mechanism underlying the phenotypic switch could be manipulated to attenuate virulence. Therefore, our group has focused on identifying and characterizing genes that regulate this switch, which led to the investigation of ABUW_1132 (1132), a highly conserved gene predicted to encode a LysR-type transcriptional regulator. ABUW_1132 was shown to be a global regulator as the expression of 74 genes was altered ≥ 2-fold in an 1132 deletion mutant. The 1132 deletion also resulted in a 16-fold decrease in VIR-O to AV-T switching, loss of 3-OH-C12-HSL secretion, and reduced surface-associated motility. Further, the deletion of 1132 in the AV-T background caused elevated capsule production, which increased colony opacity and altered the typical avirulent phenotype of translucent cells. These findings distinguish 1132 as a global regulatory gene and advance our understanding of A. baumannii’s opacity-virulence switch.