Electrical Properties in Ta2NiSe5 Film and van der Waals Heterojunction

Ternary Ta2NiSe5 is a novel electronic material having the property of an excitonic insulator at room temperature. The electrical properties of Ta2NiSe5 have not been elucidated in detail. We discuss the electronic properties in Ta2NiSe5 films and the formation of heterojunctions. Hall effect measurements showed p-type conductivity. The activation energies estimated from the temperature dependence of the carrier concentration were seen to be 0.17 eV and 0.12 eV, at approximately 300 and 400 K, respectively. It was observed that carrier generation behavior changes at the critical temperature of the excitonic insulator state (328 K). The temperature dependence of the Hall mobility below the critical temperature nearly follows the bell-shaped curves for conventional semiconductor materials. A MoS2/Ta2NiSe5 van der Waals heterojunction was fabricated using the transfer method. Rectification characteristics, which depend on the gate bias voltage, were obtained. The barrier height at the MoS2/Ta2NiSe5 heterointerface and the on/off ratio could be modulated by applying a gate bias voltage, suggesting that the carrier transport was exhibited in band-to-band flow. Our demonstration suggests that the knowledge of Ta2NiSe5 increased as an electronic material, and diode performance was successfully achieved for the electronic device applications.

An Empirical Modeling of Gate Voltage-Dependent Behaviors of Amorphous Oxide Semiconductor Thin-Film Transistors including Consideration of Contact Resistance and Disorder Effects at Room Temperature

In this paper, we present an empirical modeling procedure to capture gate bias dependency of amorphous oxide semiconductor (AOS) thin-film transistors (TFTs) while considering contact resistance and disorder effects at room temperature. From the measured transfer characteristics of a pair of TFTs where the channel layer is an amorphous In-Ga-Zn-O (IGZO) AOS, the gate voltage-dependent contact resistance is retrieved with a respective expression derived from the current–voltage relation, which follows a power law as a function of a gate voltage. This additionally allows the accurate extraction of intrinsic channel conductance, in which a disorder effect in the IGZO channel layer is embedded. From the intrinsic channel conductance, the characteristic energy of the band tail states, which represents the degree of channel disorder, can be deduced using the proposed modeling. Finally, the obtained results are also useful for development of an accurate compact TFT model, for which a gate bias-dependent contact resistance and disorder effects are essential.

High Linearity DC-38 GHz CMOS SPDT Switch

In this paper, we demonstrate a low-loss and high-linearity DC-38 GHz CMOS SPDT switch for 5G multi-band communications in 0.18 μm CMOS. Traveling-wave matching (CLCL network) is used for the output-port (ports 2 and 3) matching and isolation enhancement, while π-matching (CLC matching) is adopted for the input-port (port 1) matching. Positive/negative gate-bias is adopted for linearity enhancement because larger Pin (i.e., AC signal with larger negative Vin) is required to conduct the off-state series switch transistor. Negative-body bias is used for insertion-loss reduction because the off-state series switch transistor is closer to an open state. The SPDT switch achieves insertion loss of 0.4–1.4 dB, 3.6–4.3 dB, and 4.5–5.9 dB, respectively, for DC-6 GHz, 21–29 GHz, and 31–38 GHz. Moreover, the SPDT switch achieves isolation of 37.5–59.4 dB, 25.7–28.7 dB, and 24.3–25.2 dB, respectively, for DC-6 GHz, 21–29 GHz, and 31–38 GHz. At 28 GHz, the SPDT switch achieves remarkable input 1-dB compression point (IP1dB) of 25.6 dBm, close to the simulated one (28 dBm). To the authors’ knowledge, this is one of the best IP1dB results ever reported for millimeter-wave (mm-wave) SPDT switches.

Study of the UTBB BESOI Tunnel-FET working as a Dual-Technology Transistor

In this work, we further investigate the operation of the BESOI (Back-Enhanced Silicon-On Insulator) Dual-Technology FET, analyzing not only its behavior as a p-type Tunnel-FET when a negative back bias is applied to the struc-ture, but also as an nMOS when a positive back bias is ap-plied. The working principle is based on the generation of a channel of either holes or electrons by the back gate electric field, which can then be depleted through the front gate bias. TCAD device simulation was used for the proof of concept.