A Spiking Neuromorphic Architecture Using Gated-RRAM for Associative Memory

This work reports a spiking neuromorphic architecture for associative memory simulated in a SPICE environment using recently reported gated-RRAM (resistive random-access memory) devices as synapses alongside neurons based on complementary metal-oxide semiconductors (CMOSs). The network utilizes a Verilog A model to capture the behavior of the gated-RRAM devices within the architecture. The model uses parameters obtained from experimental gated-RRAM devices that were fabricated and tested in this work. Using these devices in tandem with CMOS neuron circuitry, our results indicate that the proposed architecture can learn an association in real time and retrieve the learned association when incomplete information is provided. These results show the promise for gated-RRAM devices for associative memory tasks within a spiking neuromorphic architecture framework.

Review of Physically Unclonable Functions (PUFs): Structures, Models, and Algorithms

Physically unclonable functions (PUFs) are now an essential component for strengthening the security of Internet of Things (IoT) edge devices. These devices are an important component in many infrastructure systems such as telehealth, commerce, industry, etc. Traditionally these devices are the weakest link in the security of the system since they have limited storage, processing, and energy resources. Furthermore they are located in unsecured environments and could easily be the target of tampering and various types of attacks. We review in this work the structure of most salient types of PUF systems such as static RAM static random access memory (SRAM), ring oscillator (RO), arbiter PUFs, coating PUFs and dynamic RAM dynamic random access memory (DRAM). We discuss statistical models for the five most common types of PUFs and identify the main parameters defining their performance. We review some of the most recent algorithms that can be used to provide stable authentication and secret key generation without having to use helper data or secure sketch algorithms. Finally we provide results showing the performance of these devices and how they depend on the authentication algorithm used and the main system parameters.

Sol-Gel Processed ZrO2 Based Forming-Free Resistive Switching Memory Devices

In this work, we fabricated ZrO2 based resistive random access memory by sol-gel spin coating technique and investigated its structural, optical and resistive switching properties. The X-ray diffraction pattern revealed that 400 °C annealed ZrO2 thin film has tetragonal structure. The optical band gap value of ZrO2 thin film obtained was 5.51 eV. The resistive switching behaviour of W/ZrO2/ITO capacitor like structure was studied. It was found that no initial electroforming process required for the device. The fabricated devices show a self-compliance bipolar resistive switching behaviour and have high on off ratio (>102). Our result suggests that solution processed ZrO2 has great potential to develop transparent and flexible resistive random access memory devices.

Impact of Thermal Boundary Resistance on Thermoelectric Effects of the Blade-Type Phase-Change Random Access Memory Device

Phase-change random access memory (PCRAM) is widely regarded as one of the most promising candidates to replace Flash memory as the next generation of non-volatile memories due to its high-speed and low-power consumption characteristics. Recent advent of the blade-type PCRAM with low programming current merit further confirms its prospects. The thermoelectric effects existing inside the PCRAM devices have always been an important factor that determines the phase-transformation kinetics due to a fact that it allows PCRAM to have electric polarity dependent characteristics. However, the potential physics governing the thermoelectric effects for blade-type PCRAM device still remains vague. We establish a three-dimensional (3D) electro-thermal and phase-transformation model to study the influences of thermal boundary resistance (TBR) and device scaling on the thermoelectric effects of the blade-type PCRAM during its “RESET” operation. Our research shows that the presence of TBR significantly improves the electric polarity-dependent characteristics of the blade-type PCRAM, and such polarity-dependent characteristic is found immune to the scaling of the device. It is therefore possible to optimize the thermoelectric effects of the blade-type PCRAM through appropriately tailoring the TBR parameters, thus further lowering resulting power consumption.

Embedded Memories for Cryogenic Applications

The ever-growing interest in cryogenic applications has prompted the investigation for energy-efficient and high-density memory technologies that are able to operate efficiently at extremely low temperatures. This work analyzes three appealing embedded memory technologies under cooling—from room temperature (300 K) down to cryogenic levels (77 K). As the temperature goes down to 77 K, six-transistor static random-access memory (6T-SRAM) presents slight improvements for static noise margin (SNM) during hold and read operations, while suffering from lower (−16%) write SNM. Gain-cell embedded DRAM (GC-eDRAM) shows significant benefits under these conditions, with read voltage margins and data retention time improved by about 2× and 900×, respectively. Non-volatile spin-transfer torque magnetic random access memory (STT-MRAM) based on single- or double-barrier magnetic tunnel junctions (MTJs) exhibit higher read voltage sensing margins (36% and 48%, respectively), at the cost of longer write access time (1.45× and 2.1×, respectively). The above characteristics make the considered memory technologies to be attractive candidates not only for high-performance computing, but also enable the possibility to bridge the gap from room-temperature to the realm of cryogenic applications that operate down to liquid helium temperatures and below.

OBET: On-the-Fly Byte-Level Error Tracking for Correcting and Detecting Faults in Unreliable DRAM Systems

With technology scaling, maintaining the reliability of dynamic random-access memory (DRAM) has become more challenging. Therefore, on-die error correction codes have been introduced to accommodate reliability issues in DDR5. However, the current solution still suffers from high overhead when a large DRAM capacity is used to deliver high performance. We present a DRAM chip architecture that can track faults at byte-level DRAM cell errors to address this problem. DRAM faults are classified as temporary or permanent in our proposed architecture, with no additional pins and with minor DRAM chip modifications. Hence, we achieve reliability comparable to that of other state-of-the-art solutions while incurring negligible performance and energy overhead. Furthermore, the faulty locations are efficiently exposed to the operating system (OS). Thus, we can significantly reduce the required scrubbing cycle by scrubbing only faulty DRAM pages while reducing the system failure probability up to 5000∼7000 times relative to conventional operation.