Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit
Latest Publications

TOTAL DOCUMENTS

104

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Published By IEEE

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Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Constant delay logic technology

Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit ◽

10.1109/asic.1994.404611 ◽

2002 ◽

Author(s):

D.W. Hall ◽

J.G. Dooley ◽

A.A. Hernandez

Keyword(s):

Constant Delay

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Tapered buffers for gate array and standard cell circuits

Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit ◽

10.1109/asic.1994.404601 ◽

2002 ◽

Cited By ~ 1

Author(s):

B.S. Cherkauer ◽

E.G. Friedman

Keyword(s):

Standard Cell ◽

Gate Array

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Design of a processor bus interface ASIC for the stream memory controller

Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit ◽

10.1109/asic.1994.404519 ◽

2002 ◽

Cited By ~ 1

Author(s):

S.W. McGee ◽

R.H. Klenke ◽

J.H. Aylor ◽

A.J. Schwab

Keyword(s):

Memory Controller

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A single-chip multiprocessor DSP solution for communications applications

Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit ◽

10.1109/asic.1994.404525 ◽

2002 ◽

Author(s):

D. Regenold

Keyword(s):

Chip Multiprocessor ◽

Single Chip

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Efficient allocation method of multiport memories in ASIC data path synthesis

Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit ◽

10.1109/asic.1994.404552 ◽

2002 ◽

Author(s):

Kwang Soo Seo ◽

Jeong Yop Lee ◽

Moon Key Lee

Keyword(s):

Data Path ◽

Efficient Allocation ◽

Allocation Method ◽

Path Synthesis

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A fault coverage-driven partial scan chain selection technique

Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit ◽

10.1109/asic.1994.404539 ◽

2002 ◽

Cited By ~ 1

Author(s):

C. Gloster ◽

S. Subramanian

Keyword(s):

Fault Coverage ◽

Partial Scan ◽

Selection Technique ◽

Scan Chain

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Implementing a digital signal processor for an electronic still camera using multiple-FPGAS

Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit ◽

10.1109/asic.1994.404563 ◽

2002 ◽

Author(s):

Shin-Shu Wang ◽

Tzu-Chiang Chung ◽

Y.T. Tsai

Keyword(s):

Digital Signal Processor ◽

Digital Signal ◽

Signal Processor

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A dual-channel analog servo-signal processor for 13 Gb tape drives

Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit ◽

10.1109/asic.1994.404615 ◽

2002 ◽

Author(s):

S. Narayan ◽

H.W. Klein

Keyword(s):

Dual Channel ◽

Servo Signal ◽

Signal Processor

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Combining the top-down approach with bottom-up advantages in logic synthesis

Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit ◽

10.1109/asic.1994.404610 ◽

2002 ◽

Cited By ~ 1

Author(s):

V. Kiefer

Keyword(s):

Logic Synthesis ◽

Top Down ◽

Bottom Up

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A 60 MHz ASIC β bit serial/parallel multiplier

Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit ◽

10.1109/asic.1994.404520 ◽

2002 ◽

Cited By ~ 1

Author(s):

F. Moogat ◽

R. Siferd

Keyword(s):

Parallel Multiplier ◽

Bit Serial

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Proceedings Seventh Annual IEEE International ASIC Conference and ExhibitLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Constant delay logic technology

Tapered buffers for gate array and standard cell circuits

Design of a processor bus interface ASIC for the stream memory controller

A single-chip multiprocessor DSP solution for communications applications

Efficient allocation method of multiport memories in ASIC data path synthesis

A fault coverage-driven partial scan chain selection technique

Implementing a digital signal processor for an electronic still camera using multiple-FPGAS

A dual-channel analog servo-signal processor for 13 Gb tape drives

Combining the top-down approach with bottom-up advantages in logic synthesis

A 60 MHz ASIC β bit serial/parallel multiplier

Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit
Latest Publications