Electro-Optical Probing for Capturing Fast-to-Rise Scan Chain Failures

The paper discusses an imaging sensor exhibiting a fast-to-rise sanity check failure from a scan chain test. The DUT was prepared for backside analysis in a portable daughter-card [1] that enabled the analyst to easily shift between testing platforms such as a standard imaging tester bench and compact scan diagnosis system [2], while being inspected under the Electro-Optical Probing (EOP) machine. To find a failing flip-flop in several-thousands long chain, broken scan chain analysis was performed to narrow down the search to a few chain links was implemented. EOP methods of fault isolation were employed to verify the location of the broken scan cell in those selected flip-flops. Finally, parallel lapping was done to confirm the location of the failing flip-flop under a SEM.

Commonality Analysis for Multiple Chain Integrity Failures

The aim of this paper is to disclose an alternative FA approach to handle complex cases, showing multiple chain failures with multiple candidates. Starting from a commonality layout analysis of candidates resulting from the diagnosis, it is possible to identify a common interconnection shared between the several candidates, already at schematic level. The effectiveness of such analysis has been successfully verified by means of a photo-emission microscopy (PEM) analysis, while running scan chain patterns and by physical analysis.

Low-Power Scan Correlation-Aware Scan Cluster Reordering for Wireless Sensor Networks

Cryptographic circuits generally are used for applications of wireless sensor networks to ensure security and must be tested in a manufacturing process to guarantee their quality. Therefore, a scan architecture is widely used for testing the circuits in the manufacturing test to improve testability. However, during scan testing, test-power consumption becomes more serious as the number of transistors and the complexity of chips increase. Hence, the scan chain reordering method is widely applied in a low-power architecture because of its ability to achieve high power reduction with a simple architecture. However, achieving a significant power reduction without excessive computational time remains challenging. In this paper, a novel scan correlation-aware scan cluster reordering is proposed to solve this problem. The proposed method uses a new scan correlation-aware clustering in order to place highly correlated scan cells adjacent to each other. The experimental results demonstrate that the proposed method achieves a significant power reduction with a relatively fast computational time compared with previous methods. Therefore, by improving the reliability of cryptography circuits in wireless sensor networks (WSNs) through significant test-power reduction, the proposed method can ensure the security and integrity of information in WSNs.

Design of a Start-Up Sequence Controller for a Mammography Machine

Mammography, which is also calledMastography, is the process of using low-energy X-rays to inspect the human breast for screening and diagnostics. The purpose of mammography is to detect breast cancer early, usually by looking for specific lumps or microcalcifications. The X-rays used are usually around 30 kVp. Excessive voltage to such a machine would be harmful to the patient. Proper monitoring of temperature and pressure needs to be ensured. To ensure this, a start-up sequence module is developed. The start-up sequence module reads the digitized voltage, pressure, and temperature reading from the sensor and asserts all the outputs to ensure that the machine is ready. The scan chain is formed of 13 scan flip-flops in this configuration. The synthesis mapped the design to 484 instances of cells in the open-source PDK technology. The design had a total area of 594 μm2, with a cell width of 0.297 μm, and a height of 0.99 μm.

Security Assessment of Dynamically Obfuscated Scan Chain Against Oracle-guided Attacks

Logic locking has emerged as a promising solution to protect integrated circuits against piracy and tampering. However, the security provided by existing logic locking techniques is often thwarted by Boolean satisfiability (SAT)-based oracle-guided attacks. Criteria for successful SAT attacks on locked circuits include: (i) the circuit under attack is fully combinational, or (ii) the attacker has scan chain access. To address the threat posed by SAT-based attacks, we adopt the dynamically obfuscated scan chain (DOSC) architecture and illustrate its resiliency against the SAT attacks when inserted into the scan chain of an obfuscated design. We demonstrate, both mathematically and experimentally, that DOSC exponentially increases the resiliency against key extraction by SAT attack and its variants. Our results show that the mathematical estimation of attack complexity correlates to the experimental results with an accuracy of 95% or better. Along with the formal proof, we model DOSC architecture to its equivalent combinational circuit and perform SAT attack to evaluate its resiliency empirically. Our experiments demonstrate that SAT attack on DOSC-inserted benchmark circuits timeout at minimal test time overhead, and while DOSC requires less than 1% area and power overhead.