Fifth International Workshop on Microprocessor Test and Verification (MTV 04) MTV-05
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Debugging sequential circuits using Boolean satisfiability

Fifth International Workshop on Microprocessor Test and Verification (MTV 04) MTV-05 ◽

10.1109/mtv.2004.7 ◽

2006 ◽

Author(s):

Moayad Fahim Ali ◽

A. Veneris ◽

S. Safarpour ◽

M. Abadir ◽

R. Drechsler ◽

...

Keyword(s):

Boolean Satisfiability ◽

Sequential Circuits

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On correlating structural tests with functional tests for speed binning of high performance design

Fifth International Workshop on Microprocessor Test and Verification (MTV 04) MTV-05 ◽

10.1109/mtv.2004.17 ◽

2006 ◽

Author(s):

J. Zeng ◽

M.S. Abadir ◽

G. Vandling ◽

L.-C. Wang ◽

S. Karako ◽

...

Keyword(s):

High Performance ◽

Functional Tests ◽

Structural Tests ◽

High Performance Design

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On the impact of structural circuit partitioning on SAT-based combinational circuit verification

Fifth International Workshop on Microprocessor Test and Verification (MTV 04) MTV-05 ◽

10.1109/mtv.2004.18 ◽

2006 ◽

Author(s):

M. Herbstritt ◽

T. Kmieciak ◽

B. Becker

Keyword(s):

Circuit Partitioning ◽

Combinational Circuit ◽

Circuit Verification ◽

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Extreme formal modeling (XFM) for hardware models

Fifth International Workshop on Microprocessor Test and Verification (MTV 04) MTV-05 ◽

10.1109/mtv.2004.8 ◽

2006 ◽

Author(s):

S. Suhaib ◽

D. Mathaikutty ◽

S. Shukla ◽

D. Berner

Keyword(s):

Formal Modeling

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A circuit level fault model for resistive shorts of MOS gate oxide

Fifth International Workshop on Microprocessor Test and Verification (MTV 04) MTV-05 ◽

10.1109/mtv.2004.1 ◽

2006 ◽

Author(s):

Xiang Lu ◽

Zhuo Li ◽

Wangqi Qiu ◽

D.M.H. Walker ◽

Weiping Shi

Keyword(s):

Fault Model ◽

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Identification of gates for covering all critical paths

Fifth International Workshop on Microprocessor Test and Verification (MTV 04) MTV-05 ◽

10.1109/mtv.2004.15 ◽

2006 ◽

Author(s):

M. Moiz Khan ◽

S. Tragoudas ◽

M. Abadir ◽

B. Liu

Keyword(s):

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Compact ATPG for concurrent SOC testing

Fifth International Workshop on Microprocessor Test and Verification (MTV 04) MTV-05 ◽

10.1109/mtv.2004.6 ◽

2006 ◽

Author(s):

A. Abdulrahman ◽

S. Tragoudas

Keyword(s):

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Micro-architecture verification for microprocessors

Fifth International Workshop on Microprocessor Test and Verification (MTV 04) MTV-05 ◽

10.1109/mtv.2004.16 ◽

2006 ◽

Author(s):

E. Bin ◽

L. Fournier

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TiGeR, the Transmeta Instruction GEneratoR: A Production Based, Pseudo Random Instruction x86 Test Generator

Fifth International Workshop on Microprocessor Test and Verification (MTV 04) MTV-05 ◽

10.1109/mtv.2004.24 ◽

2006 ◽

Author(s):

A.S. Nadkarni ◽

T. Kenville

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Functional verification of pipelined processors: a case study

Fifth International Workshop on Microprocessor Test and Verification (MTV 04) MTV-05 ◽

10.1109/mtv.2004.14 ◽

2006 ◽

Author(s):

Prabhat Mishra ◽

Nikil Dutt ◽

Yaron Kashai

Keyword(s):

Functional Verification ◽

Pipelined Processors

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