Temperature Sensitivity Analysis of Dual Material Stack Gate Oxide Source Dielectric Pocket TFET

Temperature dependence performance variation is one of the major concerns in predicting the actual electrical characteristics of the device as the bandgap of semiconducting material varies with temperature. Therefore, in this article, for the first time, the impact of temperature variations ranging from 300K to 450K on the DC, analog/ radio frequency, and linearity performance of dual material stack gate oxide-source dielectric pocket-tunnel- field-effect transistor (DMSGO-SDP-TFET) is investigated. In this regard, technology computer-aided design (TCAD) simulator is used to analyze DC, and analog/radio frequency performance parameters such as carrier concentration, energy band variation, band to band tunneling rate, IDS - VGS characteristics, transconductance (gm), cut o frequency (f T ),gain-bandwidth product (GBP), maximum oscillating frequency (fmax), transconductance frequency product (TFP), and transit time considering the impact of temperature variations. Furthermore, linearity parameters such as third-order transconductance (gm3), third-order voltage intercept point (VIP3), third-order input-interception point (IIP3), and intermodulation distortion (IMD3) are also analyzed with temperature variations as these performance parameters are significant for linear and analog/radio frequency applications. Moreover, the performance of the proposed DMSGO- SDP-TFET is compared with the conventional dual-material stack gate oxide-tunnel- field-effect transistor (DMSGO-TFET). From the comparative analysis, in terms of % per kelvin, DMSGO-SDP-TFET demonstrates lesser sensitivity towards temperature variation. Hence, the proposed DMSGO-SDP-TFET can be a suitable candidate for low power switching and analog/radio frequency applications at elevated temperatures as compared to conventional DMSGO-TFET.

Process Corresponding Implications Associated with a Conclusive Model-Fit Current-Voltage Characteristic Curves

NFinFET transistors with various fin widths (110 nm, 115 nm, and 120 nm) are put into measurements, and the data are collected. By using the modified model, the measure data is fitted. Several parameters in the formula of modified model are determined to make both the measured data and the fitting data almost as close as possible. Those parameters are listed and analyzed, including kN (proportional to channel width and gate oxide capacitor, and inversely proportional to the channel length) λ (the inverse of Early Voltage), and sometimes Vth (Threshold Voltage). By kN, the appropriate process control can be high lighted, the corresponding channel concentration can be calculated and thus many implicit physical quantities may be exploited.

Influence of Hydrogen-Nitrogen Hybrid Passivation on the Gate Oxide Film of n-Type 4H-SiC MOS Capacitors

Hydrogen-nitrogen hybrid passivation treatment for growing high-property gate oxide films by high-temperature wet oxidation, with short-time NO POA, is proposed and demonstrated. Secondary ion mass spectroscopy (SIMS) measurements show that the proposed method causes hydrogen and appropriate nitrogen atoms to accumulate in Gaussian-like distributions near the SiO2/SiC interface. Moreover, the hydrogen atoms are also incorporated into the grown SiO2 layer, with a concentration of approximately 1 × 1019 cm−3. The conductance characteristics indicate that the induced hydrogen and nitrogen passivation atoms near the interface can effectively reduce the density of interface traps and near-interface traps. The current-voltage (I-V), X-ray photoelectron spectroscopy (XPS), and time-dependent bias stress (TDBS) with ultraviolet light (UVL) irradiation results demonstrate that the grown SiO2 film with the incorporated hydrogen passivation atoms can effectively reduce the density of oxide electron traps, leading to the barrier height being improved and the leakage current being reduced.