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Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)
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TOTAL DOCUMENTS
131
(FIVE YEARS 0)
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16
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Published By IEEE
0780358090
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Latest Documents
Most Cited Documents
Contributed Authors
Related Sources
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Novel VLIW code compaction method for a 3D geometry processor
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)
◽
10.1109/cicc.2000.852729
◽
2002
◽
Cited By ~ 2
Author(s):
H. Suzuki
◽
H. Making
◽
Y. Matsuda
Keyword(s):
3D Geometry
◽
Compaction Method
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Firm IP development: methodology and deliverables
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)
◽
10.1109/cicc.2000.852723
◽
2002
◽
Cited By ~ 1
Author(s):
A. Ranjit
◽
P. Ramkumar
◽
V. Noel
Keyword(s):
Development Methodology
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An audio ADC delta-sigma modulator with 100 dB SINAD and 102 dB DR using a second-order mismatch-shaping DAC
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)
◽
10.1109/cicc.2000.852609
◽
2002
◽
Cited By ~ 8
Author(s):
E. Fogleman
◽
J. Welz
◽
I. Galton
Keyword(s):
Second Order
◽
Delta Sigma Modulator
◽
Delta Sigma
◽
Mismatch Shaping
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Physical processes of phase noise in differential LC oscillators
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)
◽
10.1109/cicc.2000.852732
◽
2002
◽
Cited By ~ 268
Author(s):
J.J. Rael
◽
A.A. Abidi
Keyword(s):
Phase Noise
◽
Physical Processes
◽
Lc Oscillators
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An analysis of the design processes required for the technology conversion of SoC intellectual property
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)
◽
10.1109/cicc.2000.852722
◽
2002
◽
Cited By ~ 1
Author(s):
J. Nash
◽
P. Smith
Keyword(s):
Intellectual Property
◽
Design Processes
◽
Technology Conversion
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A 2-V 3.7-mW delay locked-loop using recycling integrator correlators for a 5-Mcps DS-CDMA demodulator
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)
◽
10.1109/cicc.2000.852613
◽
2002
◽
Cited By ~ 1
Author(s):
Y. Fujimoto
◽
S. Kawama
◽
K. Iizuka
◽
M. Miyamoto
◽
D. Senderowicz
Keyword(s):
Delay Locked Loop
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A 1.8 GHz highly-tunable low-phase-noise CMOS VCO
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)
◽
10.1109/cicc.2000.852736
◽
2002
◽
Cited By ~ 31
Author(s):
B. De Muer
◽
N. Itoh
◽
M. Borremans
◽
M. Steyaert
Keyword(s):
Phase Noise
◽
Low Phase Noise
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A low-power CMOS super-regenerative receiver at 1 GHz
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)
◽
10.1109/cicc.2000.852641
◽
2002
◽
Cited By ~ 2
Author(s):
A. Vouilloz
◽
C. Dehollain
◽
M. Declercq
Keyword(s):
Low Power
◽
Low Power Cmos
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A 900 MHz, 2.5 mA CMOS frequency synthesizer with an automatic SC tuning loop
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)
◽
10.1109/cicc.2000.852689
◽
2002
◽
Cited By ~ 3
Author(s):
Tsung-Hsien Lin
◽
W.J. Kaiser
Keyword(s):
Frequency Synthesizer
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New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)
◽
10.1109/cicc.2000.852648
◽
2002
◽
Cited By ~ 214
Author(s):
Y. Cao
◽
T. Sato
◽
M. Orshansky
◽
D. Sylvester
◽
C. Hu
Keyword(s):
Circuit Simulation
◽
New Paradigm
◽
Interconnect Modeling
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