Proceedings of the 2005 International Conference on Microelectronic Test Structures, 2005. ICMTS 2005.

Test structures for the characterization of deep trench isolation [The following paper has been withdrawn by the authors]

Proceedings of the 2005 International Conference on Microelectronic Test Structures, 2005. ICMTS 2005. ◽

10.1109/icmts.2005.1452209 ◽

2005 ◽

Author(s):

S. Hausser ◽

R. Albus ◽

H. Schligtenhorst

Keyword(s):

Deep Trench ◽

Trench Isolation

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Extraction of critical dimension reference feature CDs from new test structure using HRTEM imaging

Proceedings of the 2005 International Conference on Microelectronic Test Structures, 2005. ICMTS 2005. ◽

10.1109/icmts.2005.1452203 ◽

2005 ◽

Cited By ~ 3

Author(s):

R.A. Allen ◽

A. Hunt ◽

C.E. Murabito ◽

B. Park ◽

W.F. Guthrie ◽

...

Keyword(s):

Critical Dimension ◽

Test Structure ◽

Reference Feature

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Capacitance characterization in integrated circuit development: the intimate relationship of test structure design, equivalent circuit and measurement methodology

Proceedings of the 2005 International Conference on Microelectronic Test Structures, 2005. ICMTS 2005. ◽

10.1109/icmts.2005.1452268 ◽

2005 ◽

Cited By ~ 12

Author(s):

G.A. Brown

Keyword(s):

Equivalent Circuit ◽

Integrated Circuit ◽

Intimate Relationship ◽

Structure Design ◽

Test Structure ◽

Measurement Methodology ◽

Circuit Development ◽

Relationship Of

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Novel realistic short structure construction for parasitic resistance de-embedding and on-wafer inductor characterization

Proceedings of the 2005 International Conference on Microelectronic Test Structures, 2005. ICMTS 2005. ◽

10.1109/icmts.2005.1452260 ◽

2005 ◽

Cited By ~ 4

Author(s):

J. Tao ◽

P. Findley ◽

G.A. Rezvani

Keyword(s):

Parasitic Resistance

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Multi-purpose EM test structure with electrical verification of the failure spot demonstrated using SWEAT for fast wafer level reliability monitoring

Proceedings of the 2005 International Conference on Microelectronic Test Structures, 2005. ICMTS 2005. ◽

10.1109/icmts.2005.1452232 ◽

2005 ◽

Author(s):

A. Pietsch ◽

A. Martin ◽

J. Fazekas

Keyword(s):

Test Structure ◽

Wafer Level ◽

Reliability Monitoring

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A novel test fixture with enhanced signal port isolation capability for on-wafer microwave measurements

Proceedings of the 2005 International Conference on Microelectronic Test Structures, 2005. ICMTS 2005. ◽

10.1109/icmts.2005.1452257 ◽

2005 ◽

Cited By ~ 2

Author(s):

T. Kaija ◽

E.O. Ristolainen

Keyword(s):

Microwave Measurements ◽

Test Fixture

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RF-ESD design and measurement of CMOS LNAs: a comparison between diode and inductive protection

Proceedings of the 2005 International Conference on Microelectronic Test Structures, 2005. ICMTS 2005. ◽

10.1109/icmts.2005.1452256 ◽

2005 ◽

Cited By ~ 1

Author(s):

P. Leroux ◽

M. Steyaert

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Design and implementation of an ultra high precision parametric mismatch measurement system

Proceedings of the 2005 International Conference on Microelectronic Test Structures, 2005. ICMTS 2005. ◽

10.1109/icmts.2005.1452249 ◽

2005 ◽

Author(s):

T. Ewert ◽

H. Tuinhoutt ◽

N. Wils ◽

J. Olsson

Keyword(s):

High Precision ◽

Measurement System ◽

Design And Implementation

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An improved LDMOS transistor model that accurately predicts capacitance for all bias conditions

Proceedings of the 2005 International Conference on Microelectronic Test Structures, 2005. ICMTS 2005. ◽

10.1109/icmts.2005.1452226 ◽

2005 ◽

Cited By ~ 14

Author(s):

S.F. Frere ◽

P. Moens ◽

B. Desoete ◽

Wojciechowski D ◽

A.J. Walton

Keyword(s):

Transistor Model

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Substrate isolation in 0.18um CMOS technology

Proceedings of the 2005 International Conference on Microelectronic Test Structures, 2005. ICMTS 2005. ◽

10.1109/icmts.2005.1452244 ◽

2005 ◽

Cited By ~ 3

Author(s):

G.A. Rezvani ◽

Jon Tao

Keyword(s):

Cmos Technology

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Proceedings of the 2005 International Conference on Microelectronic Test Structures, 2005. ICMTS 2005.
Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Test structures for the characterization of deep trench isolation [The following paper has been withdrawn by the authors]

Extraction of critical dimension reference feature CDs from new test structure using HRTEM imaging

Capacitance characterization in integrated circuit development: the intimate relationship of test structure design, equivalent circuit and measurement methodology

Novel realistic short structure construction for parasitic resistance de-embedding and on-wafer inductor characterization

Multi-purpose EM test structure with electrical verification of the failure spot demonstrated using SWEAT for fast wafer level reliability monitoring

A novel test fixture with enhanced signal port isolation capability for on-wafer microwave measurements

RF-ESD design and measurement of CMOS LNAs: a comparison between diode and inductive protection

Design and implementation of an ultra high precision parametric mismatch measurement system

An improved LDMOS transistor model that accurately predicts capacitance for all bias conditions

Substrate isolation in 0.18um CMOS technology

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Proceedings of the 2005 International Conference on Microelectronic Test Structures, 2005. ICMTS 2005.Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Test structures for the characterization of deep trench isolation [The following paper has been withdrawn by the authors]

Extraction of critical dimension reference feature CDs from new test structure using HRTEM imaging

Capacitance characterization in integrated circuit development: the intimate relationship of test structure design, equivalent circuit and measurement methodology

Novel realistic short structure construction for parasitic resistance de-embedding and on-wafer inductor characterization

Multi-purpose EM test structure with electrical verification of the failure spot demonstrated using SWEAT for fast wafer level reliability monitoring

A novel test fixture with enhanced signal port isolation capability for on-wafer microwave measurements

RF-ESD design and measurement of CMOS LNAs: a comparison between diode and inductive protection

Design and implementation of an ultra high precision parametric mismatch measurement system

An improved LDMOS transistor model that accurately predicts capacitance for all bias conditions

Substrate isolation in 0.18um CMOS technology

Proceedings of the 2005 International Conference on Microelectronic Test Structures, 2005. ICMTS 2005.
Latest Publications