2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC)
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Published By IEEE

9781467317078, 9781467317085

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Drain-conductance optimization in nanowire TFETs

2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC) ◽

10.1109/essderc.2012.6343344 ◽

2012 ◽

Cited By ~ 11

Author(s):

E. Gnani ◽

S. Reggiani ◽

A. Gnudi ◽

G. Baccarani

Keyword(s):

Drain Conductance

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Author index

2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC) ◽

10.1109/essderc.2012.6343404 ◽

2012 ◽

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On the UTBB SOI MOSFET performance improvement in quasi-double-gate regime

2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC) ◽

10.1109/essderc.2012.6343379 ◽

2012 ◽

Cited By ~ 9

Author(s):

V. Kilchytska ◽

D. Flandre ◽

F. Andrieu

Keyword(s):

Performance Improvement ◽

Double Gate ◽

Soi Mosfet

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Comprehensive statistical comparison of RTN and BTI in deeply scaled MOSFETs by means of 3D ‘atomistic’ simulation

2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC) ◽

10.1109/essderc.2012.6343345 ◽

2012 ◽

Cited By ~ 8

Author(s):

Salvatore M. Amoroso ◽

Louis Gerrer ◽

Stanislav Markov ◽

Fikru Adamu-Lema ◽

Asen Asenov

Keyword(s):

Statistical Comparison

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Two-step annealing effects on ultrathin EOT higher-k (k = 40) ALD-HfO2 gate stacks

2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC) ◽

10.1109/essderc.2012.6343338 ◽

2012 ◽

Author(s):

Yukinori Morita ◽

Shinji Migita ◽

Wataru Mizubayashi ◽

Meishoku Masahara ◽

Hiroyuki Ota

Keyword(s):

Gate Stacks ◽

Annealing Effects

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Variability aware cell library optimization for reliable sub-threshold operation

2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC) ◽

10.1109/essderc.2012.6343333 ◽

2012 ◽

Cited By ~ 1

Author(s):

Tobias Gemmeke ◽

Maryam Ashouei

Keyword(s):

Cell Library

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Study of carrier transport in strained and unstrained SOI tri-gate and omega-gate Si-nanowire MOSFETs

2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC) ◽

10.1109/essderc.2012.6343336 ◽

2012 ◽

Cited By ~ 10

Author(s):

M. Koyama ◽

M. Casse ◽

R. Coquand ◽

S. Barraud ◽

H. Iwai ◽

...

Keyword(s):

Carrier Transport ◽

Si Nanowire ◽

Nanowire Mosfets

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Top-down fabricated ZnO nanowire transistors for application in biosensors

2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC) ◽

10.1109/essderc.2012.6343352 ◽

2012 ◽

Cited By ~ 4

Author(s):

S. M. Sultan ◽

K. Sun ◽

M. R. R. de Planque ◽

P. Ashburn ◽

H. M. H. Chong

Keyword(s):

Zno Nanowire ◽

Top Down ◽

Nanowire Transistors

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Design challenges for nano-scale devices

2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC) ◽

10.1109/essderc.2012.6343335 ◽

2012 ◽

Author(s):

Marc Belleville ◽

Olivier Thomas ◽

Alexandre Valentian ◽

Fabien Clermidy

Keyword(s):

Nano Scale ◽

Design Challenges

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Sensitivity-based investigation of threshold voltage variability in 32-nm flash memory cells

2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC) ◽

10.1109/essderc.2012.6343347 ◽

2012 ◽

Author(s):

Valentina Bonfiglio ◽

Giuseppe Iannaccone

Keyword(s):

Threshold Voltage ◽

Flash Memory ◽

Memory Cells

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2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Drain-conductance optimization in nanowire TFETs

Author index

On the UTBB SOI MOSFET performance improvement in quasi-double-gate regime

Comprehensive statistical comparison of RTN and BTI in deeply scaled MOSFETs by means of 3D ‘atomistic’ simulation

Two-step annealing effects on ultrathin EOT higher-k (k = 40) ALD-HfO2 gate stacks

Variability aware cell library optimization for reliable sub-threshold operation

Study of carrier transport in strained and unstrained SOI tri-gate and omega-gate Si-nanowire MOSFETs

Top-down fabricated ZnO nanowire transistors for application in biosensors

Design challenges for nano-scale devices

Sensitivity-based investigation of threshold voltage variability in 32-nm flash memory cells

2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC)
Latest Publications