Interface Optimization and Transport Modulation of Sm2O3/InP Metal Oxide Semiconductor Capacitors with Atomic Layer Deposition-Derived Laminated Interlayer

In this paper, the effect of atomic layer deposition-derived laminated interlayer on the interface chemistry and transport characteristics of sputtering-deposited Sm2O3/InP gate stacks have been investigated systematically. Based on X-ray photoelectron spectroscopy (XPS) measurements, it can be noted that ALD-derived Al2O3 interface passivation layer significantly prevents the appearance of substrate diffusion oxides and substantially optimizes gate dielectric performance. The leakage current experimental results confirm that the Sm2O3/Al2O3/InP stacked gate dielectric structure exhibits a lower leakage current density than the other samples, reaching a value of 2.87 × 10−6 A/cm2. In addition, conductivity analysis shows that high-quality metal oxide semiconductor capacitors based on Sm2O3/Al2O3/InP gate stacks have the lowest interfacial density of states (Dit) value of 1.05 × 1013 cm−2 eV−1. The conduction mechanisms of the InP-based MOS capacitors at low temperatures are not yet known, and to further explore the electron transport in InP-based MOS capacitors with different stacked gate dielectric structures, we placed samples for leakage current measurements at low varying temperatures (77–227 K). Based on the measurement results, Sm2O3/Al2O3/InP stacked gate dielectric is a promising candidate for InP-based metal oxide semiconductor field-effect-transistor devices (MOSFET) in the future.

Direct growth of orthorhombic Hf0.5Zr0.5O2 thin films for hysteresis-free MoS2 negative capacitance field-effect transistors

Herein, the direct growth of polar orthorhombic phase in Hf0.5Zr0.5O2 (HZO) thin films is reported using Pulsed Laser Deposition (PLD). The growth of HZO onto a preheated (700 °C) silicon substrate mimics the rapid thermal annealing, which allows the formation of smaller crystallites (~9.7 nm) with large surface energy leading to the stabilization of metastable orthorhombic phase. Unlike atomic layer deposition (ALD) of HZO, PLD is more advantageous for depositing highly crystalline thin films through optimized parameters, such as laser fluence and background gas pressure. Further, the PLD-HZO is integrated with HfO2 dielectric and the resulting gate stacks have been used in the bottom gate FET architecture-‘Si//PLD-HZO/HfO2/MoS2//Ti/Au’. The NCFETs have yielded a sub-thermionic subthreshold swing (SSfor = 33.03 ± 8.7 mV/dec. and SSrev = 36.4 ± 7.7 mV/dec.) and a negligible hysteresis (~28 mV), which is capable in realizing low power integrated digital/analog circuits.

Atomic-scale ferroic HfO2-ZrO2 superlattice gate stack for advanced transistors

With the scaling of lateral dimensions in advanced transistors, an increased gate capacitance is desirable both to retain the control of the gate electrode over the channel and to reduce the operating voltage. This led to the adoption of high-κ dielectric HfO2 in the gate stack in 2008, which remains as the material of choice to date. Here, we report HfO2-ZrO2 superlattice heterostructures as a gate stack, stabilized with mixed ferroelectric-antiferroelectric order, directly integrated onto Si transistors and scaled down to ~ 20 Å, the same gate oxide thickness required for high performance transistors. The overall EOT (equivalent oxide thickness) in metal-oxide-semiconductor capacitors is equivalent to ~ 6.5 Å effective SiO2 thickness, which is, counterintuitively, even smaller than the interfacial SiO2 thickness (8.0-8.5 Å) itself. Such a low effective oxide thickness and the resulting large capacitance cannot be achieved in conventional HfO2-based high-κ dielectric gate stacks without scavenging the interfacial SiO2, which has adverse effects on the electron transport and gate leakage current. Accordingly, our gate stacks, which do not require such scavenging, provide substantially lower leakage current and no mobility degradation. Therefore, our work demonstrates that HfO2-ZrO2 multilayers with competing ferroelectric-antiferroelectric order, stabilized in the 2 nm thickness regime, provides a new path towards advanced gate oxide stacks in electronic devices beyond the conventional HfO2-based high-κ dielectrics.