On the UTBB SOI MOSFET performance improvement in quasi-double-gate regime

2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC) ◽

10.1109/essderc.2012.6343379 ◽

2012 ◽

Author(s):

V. Kilchytska ◽

D. Flandre ◽

F. Andrieu

Keyword(s):

Performance Improvement ◽

Double Gate ◽

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Performance Scrutiny of Source and Drain-Engineered Dual-Material Double-Gate (DMDG) SOI MOSFET with Various High-K

Advances in Intelligent Systems and Computing - Intelligent Engineering Informatics ◽

10.1007/978-981-10-7566-7_53 ◽

2018 ◽

pp. 533-539

Author(s):

Himanshu Yadav ◽

R. K. Chauhan

Keyword(s):

Double Gate ◽

High K ◽

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32nm technology node Double-Gate SOI MOSFET using SiO2 gate stacks

2006 International Workshop on Nano CMOS ◽

10.1109/iwnc.2006.4570975 ◽

2006 ◽

Author(s):

Enrico Sangiorgi ◽

Nicola Barin ◽

Marco Braccioli ◽

Claudio Fiegna

Keyword(s):

Double Gate ◽

Gate Stacks ◽

Technology Node

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Parameter characterization of double gate ultra-thin SOI MOSFET

Proceedings. IEEE International SOI Conference ◽

10.1109/soi.1994.514220 ◽

2002 ◽

Author(s):

Jyi-Tsong Lin

Keyword(s):

Double Gate ◽

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Simulation analysis of a novel fully depleted SOI MOSFET: Electrical and thermal performance improvement through trapezoidally doped channel and silicon–nitride buried insulator

Physica E Low-dimensional Systems and Nanostructures ◽

10.1016/j.physe.2015.01.012 ◽

2015 ◽

Vol 69 ◽

pp. 27-33 ◽

Author(s):

Hadi Shahnazarisani ◽

Saeed Mohammadi

Keyword(s):

Silicon Nitride ◽

Performance Improvement ◽

Thermal Performance ◽

Simulation Analysis ◽

Fully Depleted ◽

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A Simple Method to Fabricate Double-Gate SOI MOSFET with Diffusion Layer on Bulk Silicon Wafer as the Bottom Gate

10.7567/ssdm.2001.c-4-4 ◽

2001 ◽

Author(s):

Xinnan Lin ◽

Chuguang Feng ◽

Shengdong Zhang ◽

Wai-Hung Ho ◽

Mansun Chan

Keyword(s):

Silicon Wafer ◽

Diffusion Layer ◽

Double Gate ◽

Bulk Silicon ◽

Simple Method ◽

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Double-gate SOI MOSFET fabrication from bulk silicon wafer

2001 IEEE International SOI Conference Proceedings (Cat No 01CH37207) SOI-01 ◽

10.1109/soic.2001.958001 ◽

2002 ◽

Author(s):

Xinnan Lin ◽

Chuguang Feng ◽

Shengdong Zhang ◽

Wai-Hung Ho ◽

Mansun Chan

Keyword(s):

Silicon Wafer ◽

Double Gate ◽

Bulk Silicon ◽

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Semiconductor thickness effects in the double-gate SOI MOSFET

IEEE Transactions on Electron Devices ◽

10.1109/16.669563 ◽

1998 ◽

Vol 45 (5) ◽

pp. 1127-1134 ◽

Author(s):

B. Majkusiak ◽

T. Janik ◽

J. Walczak

Keyword(s):

Double Gate ◽

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Threshold voltage modeling of deep-submicron double-gate fully-depleted SOI MOSFET

2007 7th International Conference on ASIC ◽

10.1109/icasic.2007.4415838 ◽

2007 ◽

Author(s):

Zhang Zhengfan ◽

Fang Jian ◽

Li Ruzhang ◽

Zhang Zhengyuan ◽

Li Zhaoji

Keyword(s):

Threshold Voltage ◽

Deep Submicron ◽

Double Gate ◽

Fully Depleted ◽

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A high performance double-gate SOI MOSFET using lateral solid phase epitaxy

IEEE International SOI Conference SOI-02 ◽

10.1109/soi.2002.1044403 ◽

2002 ◽

Author(s):

Haitao Liu ◽

Zhibin Xiong ◽

Sin ◽

Peiqi Xuan ◽

Bokor

Keyword(s):

High Performance ◽

Solid Phase ◽

Double Gate ◽

Solid Phase Epitaxy ◽

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Subthreshold Performance of Double-gate Accumulation-mode P-channel SOI MOSFET

2007 International Conference on Microwave and Millimeter Wave Technology ◽

10.1109/icmmt.2007.381457 ◽

2007 ◽

Author(s):

Zhang Zhengfan ◽

Li Zhaoji ◽

Tan Kaizhou ◽

Zhang Jiabin ◽

Li Kaicheng

Keyword(s):

Double Gate ◽

Accumulation Mode

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