Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)
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Published By IEEE Comput. Soc

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Panel on advanced embedded memory technologies

Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002) ◽

10.1109/mtdt.2002.1029782 ◽

2005 ◽

Author(s):

B.F. Cockburn

Keyword(s):

Embedded Memory

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A novel memory array based on an annular single-poly EPROM cell for use in standard CMOS technology

Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002) ◽

10.1109/mtdt.2002.1029775 ◽

2003 ◽

Cited By ~ 1

Author(s):

C. Dray ◽

P. Gendrier

Keyword(s):

Cmos Technology ◽

Memory Array

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A simulator for evaluating redundancy analysis algorithms of repairable embedded memories

Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002) ◽

10.1109/mtdt.2002.1029766 ◽

2003 ◽

Cited By ~ 20

Author(s):

Rei-Fu Huang ◽

Jin-Fu Li ◽

Jen-Chieh Yeh ◽

Cheng-Wen Wu

Keyword(s):

Redundancy Analysis ◽

Embedded Memories

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Fast and compact error correcting scheme for reliable multilevel flash memories

Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002) ◽

10.1109/mtdt.2002.1029759 ◽

2003 ◽

Cited By ~ 4

Author(s):

D. Rossi ◽

C. Metra ◽

B. Ricco

Keyword(s):

Flash Memories

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A silicon-based yield gain evaluation methodology for embedded-SRAMs with different redundancy scenarios

Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002) ◽

10.1109/mtdt.2002.1029764 ◽

2003 ◽

Cited By ~ 2

Author(s):

E. Rondey ◽

Y. Tellier ◽

S. Borri

Keyword(s):

Evaluation Methodology ◽

Yield Gain ◽

Silicon Based

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Decreasing EEPROM programming bias with negative voltage, reliability impact

Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002) ◽

10.1109/mtdt.2002.1029781 ◽

2003 ◽

Cited By ~ 1

Author(s):

R. Laffont ◽

J. Razafindramora ◽

P. Canet ◽

R. Bouchakour ◽

J.M. Mirabel

Keyword(s):

Negative Voltage

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Defect-oriented analysis of memory BIST tests

Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002) ◽

10.1109/mtdt.2002.1029756 ◽

2003 ◽

Cited By ~ 4

Author(s):

A. Jee

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A BIST-based solution for the diagnosis of embedded memories adopting image processing techniques

Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002) ◽

10.1109/mtdt.2002.1029757 ◽

2003 ◽

Cited By ~ 2

Author(s):

D. Appello ◽

A. Fudoli ◽

V. Tancorre ◽

F. Corno ◽

M. Rebaudengo ◽

...

Keyword(s):

Image Processing ◽

Image Processing Techniques ◽

Processing Techniques ◽

Embedded Memories

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Fault tolerant insertion and verification: a case study

Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002) ◽

10.1109/mtdt.2002.1029762 ◽

2003 ◽

Cited By ~ 1

Author(s):

A. Manzone ◽

D. De Costantini

Keyword(s):

Fault Tolerant

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Design and test of a 9-port SRAM for a 100 Gb/s STS-1 switch

Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002) ◽

10.1109/mtdt.2002.1029767 ◽

2003 ◽

Author(s):

R. Gibbins ◽

R.D. Adams ◽

T. Eckenrode ◽

M. Ouellette ◽

Yuejian Wu

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Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE Comput. Soc

Panel on advanced embedded memory technologies

A novel memory array based on an annular single-poly EPROM cell for use in standard CMOS technology

A simulator for evaluating redundancy analysis algorithms of repairable embedded memories

Fast and compact error correcting scheme for reliable multilevel flash memories

A silicon-based yield gain evaluation methodology for embedded-SRAMs with different redundancy scenarios

Decreasing EEPROM programming bias with negative voltage, reliability impact

Defect-oriented analysis of memory BIST tests

A BIST-based solution for the diagnosis of embedded memories adopting image processing techniques

Fault tolerant insertion and verification: a case study

Design and test of a 9-port SRAM for a 100 Gb/s STS-1 switch

Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)
Latest Publications