The CDAU — a common data acquisition unit for the radiation imaging detectors at HIRFL-CSR

A common data acquisition unit (CDAU) has been designed for data transmission in the radiation imaging detectors in the Heavy Ion Facility in Lanzhou (HIRFL). With a bandwidth of 64 Gbps, this CDAU can meet the need for most of the experiment. The CDAU can connect four front-end readout cards (FECs) through optical links for data collection, packaging, and transmission. This CDAU is based on the PCI Express (PCIe) Gen3 bus, using Xilinx Kintex Ultrascale series FPGA, combined with the periphery circuits design to complete the data acquisition system. This paper will discuss the design and performance of the CDAU.

Development of a PXI Express Peripheral Module and Data Transfer Platform

<p>Magritek, a company who specialise in NMR and MRI devices, required a new backplane communication solution for transmission of data. Possible options were evaluated and it was decided to move to the PXI Express instrumentation standard. As a first step of moving to this system, an FPGA based PXI Express Peripheral Module was designed and constructed. In order to produce this device, details on PXI Express boards and the signals required were researched, and schematics produced. These were then passed onto the board designer who incorporated the design with other design work at Magritek to produce a PXI Express Peripheral Module for use as an NMR transceiver board. With the board designed, the FPGA was configured to provide PXI Express functionality. This was designed to allow PCI Express transfers at high data speeds using Direct Memory Access (DMA). The PXI Express Peripheral board was then tested and found to function correctly, providing Memory Write speeds of 228 MB/s and Memory Read speeds of 162 MB/s. Also, to provide a test system for this physical and FPGA design, backplanes were designed to test communication between PXI Express modules.</p>

Development of a PXI Express Peripheral Module and Data Transfer Platform

<p>Magritek, a company who specialise in NMR and MRI devices, required a new backplane communication solution for transmission of data. Possible options were evaluated and it was decided to move to the PXI Express instrumentation standard. As a first step of moving to this system, an FPGA based PXI Express Peripheral Module was designed and constructed. In order to produce this device, details on PXI Express boards and the signals required were researched, and schematics produced. These were then passed onto the board designer who incorporated the design with other design work at Magritek to produce a PXI Express Peripheral Module for use as an NMR transceiver board. With the board designed, the FPGA was configured to provide PXI Express functionality. This was designed to allow PCI Express transfers at high data speeds using Direct Memory Access (DMA). The PXI Express Peripheral board was then tested and found to function correctly, providing Memory Write speeds of 228 MB/s and Memory Read speeds of 162 MB/s. Also, to provide a test system for this physical and FPGA design, backplanes were designed to test communication between PXI Express modules.</p>

Một Giải Pháp Bảo Mật Dữ Liệu PCI-Express Sử Dụng Công Nghệ FPGA

Abstract—With high-speed data transmission such as PCI-Express, the cryptographic intervention in the transmission line, which does not affect the data transmission process but still ensures the data transmission rate of the protocol, will be the foundation to develop cryptographic applications using PCI-Express protocol. In this article, a technical solution to capture the data packet of the PCI-Express protocol using FPGA technology will be presented. Using the standard library of PCI-Express on the computer to connect to the FPGA board, on which organizing the data according to the standard of PCI-Express protocol, at the same time to cryptographic intervening on the line. Thus, plaintext will be transmitted from the computer to the FPGA board via PCI-Express interface, then it will be organized, cryptographic intervened and transmitted back to the computer.Tóm tắt—Với đường truyền dữ liệu tốc độ cao như PCI-Express, việc can thiệp mật mã vào trong đường truyền để không ảnh hưởng đến quá trình truyền dữ liệu mà vẫn đảm bảo được tốc độ truyền dữ liệu của giao thức mang lại sẽ là cơ sở để phát triển các ứng dụng mật mã sử dụng giao thức PCI-Express. Trong bài báo này sẽ trình bày một giải pháp kỹ thuật bắt gói tin dữ liệu của giao thức PCI-Express sử dụng công nghệ FPGA. Sử dụng bộ thư viện chuẩn PCI-Express trên máy tính để thực hiện kết nối tới bo mạch FPGA, qua đó trên FPGA thực hiện tổ chức dữ liệu theo chuẩn giao thức PCI-Express, đồng thời tổ chức can thiệp mật mã trên đường truyền. Như vậy, dữ liệu rõ sẽ được truyền từ máy tính xuống bo mạch FPGA thông qua giao tiếp PCI-Express, sau đó được tổ chức, can thiệp mật mã và truyền lại cho máy tính.

Remote Access NVMe SSD via NTB

NVMe SSDs are deployed in data centers for applications with high performance, but its capacity and bandwidth are often underutilized. Remote access NVMe SSD enables flexible scaling and high utilization of Flash capacity and bandwidth within data centers. The current issue of remote access NVMe SSD has significant performance overheads. The research focuses on remote access NVMe SSD via NTB (non-transparent bridge). NTB is a type of PCI-Express; its memory mapping technology can allow to access memory belonging to peer servers. NVMe SSD supports multiple I/O queues to maximize the I/O parallel processing of flash; hence, NVMe SSD can provide significant performance when comparing with traditional hard drives. The research proposes a novel design based on features of NTB memory mapping and NVMe SSD multiple I/O queues. The remote and local servers can access the same NVMe SSD concurrently. The experimental results show the performance of remote access NVMe SSD can approach the local access. It is significantly excellent and proved feasible.

A 1.93-pJ/Bit PCI Express Gen4 PHY Transmitter with On-Chip Supply Regulators in 28 nm CMOS

This paper presents a fully integrated Peripheral Component Interconnect (PCI) Express (PCIe) Gen4 physical layer (PHY) transmitter. The prototype chip is fabricated in a 28 nm low-power CMOS process, and the active area of the proposed transmitter is 0.23 mm2. To enable voltage scaling across wide operating rates from 2.5 Gb/s to 16 Gb/s, two on-chip supply regulators are included in the transmitter. At the same time, the regulators maintain the output impedance of the transmitter to meet the return loss specification of the PCIe, by including replica segments of the output driver and reference resistance in the regulator loop. A three-tap finite-impulse-response (FIR) equalization is implemented and, therefore, the transmitter provides more than 9.5 dB equalization which is required in the PCIe specification. At 16 Gb/s, the prototype chip achieves energy efficiency of 1.93 pJ/bit including all the interface, bias, and built-in self-test circuits.