2010 Conference on Design and Architectures for Signal and Image Processing (DASIP)
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Published By IEEE

9781424487349

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RVC: A multi-decoder CAL Composer tool

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) ◽

10.1109/dasip.2010.5706258 ◽

2010 ◽

Cited By ~ 14

Author(s):

F. Palumbo ◽

D. Pani ◽

E. Manca ◽

L. Raffo ◽

M. Mattavelli ◽

...

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A dynamically reconfigurable asynchronous processor for low power applications

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) ◽

10.1109/dasip.2010.5706249 ◽

2010 ◽

Cited By ~ 1

Author(s):

K.A. Fawaz ◽

T. Arslan ◽

S. Khawam ◽

M. Muir ◽

I. Nousias ◽

...

Keyword(s):

Low Power ◽

Dynamically Reconfigurable

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Camera-based system for tracking and position estimation of humans

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) ◽

10.1109/dasip.2010.5706247 ◽

2010 ◽

Cited By ~ 5

Author(s):

Robert Hartmann ◽

Fadi Al Machot ◽

Philipp Mahr ◽

Christophe Bobda

Keyword(s):

Position Estimation

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An in-band reconfigurable network node based on a heterogeneous platform

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) ◽

10.1109/dasip.2010.5706240 ◽

2010 ◽

Cited By ~ 1

Author(s):

E. Markert ◽

E. Billich ◽

C. Tischendorf ◽

U. Pross ◽

T. Leibelt ◽

...

Keyword(s):

Network Node ◽

Heterogeneous Platform

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Automated generation of an efficient MPEG-4 Reconfigurable Video Coding decoder implementation

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) ◽

10.1109/dasip.2010.5706274 ◽

2010 ◽

Cited By ~ 1

Author(s):

Ruirui Gu ◽

Jonathan Piat ◽

Mickael Raulet ◽

Jorn W. Janneck ◽

Shuvra S. Bhattacharyya

Keyword(s):

Video Coding ◽

Automated Generation ◽

Reconfigurable Video Coding

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A new single-error correction scheme based on self-diagnosis residue number arithmetic

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) ◽

10.1109/dasip.2010.5706242 ◽

2010 ◽

Cited By ~ 2

Author(s):

Yangyang Tang ◽

Emmanuel Boutillon ◽

Christophe Jego ◽

Michel Jezequel

Keyword(s):

Error Correction ◽

Single Error ◽

Correction Scheme ◽

Residue Number

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Generation of static tables in embedded memory with dense scheduling

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) ◽

10.1109/dasip.2010.5706253 ◽

2010 ◽

Cited By ~ 2

Author(s):

Benot Miramond ◽

Liliana Cucu-Grosjean

Keyword(s):

Embedded Memory

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GPU architecture evaluation for multispectral and hyperspectral image analysis

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) ◽

10.1109/dasip.2010.5706255 ◽

2010 ◽

Cited By ~ 7

Author(s):

Virginie Fresse ◽

Dominique Houzet ◽

Christophe Gravier

Keyword(s):

Image Analysis ◽

Hyperspectral Image ◽

Hyperspectral Image Analysis ◽

Architecture Evaluation ◽

Gpu Architecture

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Real-time classification based on color and texture attributes on an FPGA-based architecture

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) ◽

10.1109/dasip.2010.5706272 ◽

2010 ◽

Cited By ~ 8

Author(s):

Mario-Alberto Ibarra-Manzano ◽

Michel Devy ◽

Jean-Louis Boizard

Keyword(s):

Real Time ◽

Texture Attributes ◽

Real Time Classification

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High speed Fp multipliers and adders on FPGA platform

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) ◽

10.1109/dasip.2010.5706241 ◽

2010 ◽

Cited By ~ 7

Author(s):

Santosh Ghosh ◽

Debdeep Mukhopadhyay ◽

Dipanwita Roy Chowdhury

Keyword(s):

High Speed

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2010 Conference on Design and Architectures for Signal and Image Processing (DASIP)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

RVC: A multi-decoder CAL Composer tool

A dynamically reconfigurable asynchronous processor for low power applications

Camera-based system for tracking and position estimation of humans

An in-band reconfigurable network node based on a heterogeneous platform

Automated generation of an efficient MPEG-4 Reconfigurable Video Coding decoder implementation

A new single-error correction scheme based on self-diagnosis residue number arithmetic

Generation of static tables in embedded memory with dense scheduling

GPU architecture evaluation for multispectral and hyperspectral image analysis

Real-time classification based on color and texture attributes on an FPGA-based architecture

High speed Fp multipliers and adders on FPGA platform

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP)
Latest Publications