2015 IEEE 24th Asian Test Symposium (ATS)
Latest Publications

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9781467397391

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Design-for-testability in reversible logic circuits based on bit-swapping

2015 IEEE 24th Asian Test Symposium (ATS) ◽

10.1109/ats.2015.8125669 ◽

2015 ◽

Author(s):

Joyati Mondal ◽

Debesh K. Das ◽

Bhargab B. Bhattacharya

Keyword(s):

Design For Testability ◽

Logic Circuits ◽

Reversible Logic

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A Lightweight Timing Channel Protection for Shared Memory Controllers

2015 IEEE 24th Asian Test Symposium (ATS) ◽

10.1109/ats.2015.17 ◽

2015 ◽

Author(s):

Guopei Liu ◽

Ying Wang ◽

Sen Li ◽

Huawei Li ◽

Xiaowei Li

Keyword(s):

Shared Memory ◽

Timing Channel

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Diagnostic Tests and Diagnosis for Delay Faults Using Path Segmentation

2015 IEEE 24th Asian Test Symposium (ATS) ◽

10.1109/ats.2015.32 ◽

2015 ◽

Author(s):

Tino Flenker ◽

Andre Sulflow ◽

Goerschwin Fey

Keyword(s):

Diagnostic Tests ◽

Delay Faults ◽

Path Segmentation

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A Novel Scan Segmentation Design for Power Controllability and Reduction in At-Speed Test

2015 IEEE 24th Asian Test Symposium (ATS) ◽

10.1109/ats.2015.9 ◽

2015 ◽

Cited By ~ 2

Author(s):

Zhou Jiang ◽

Dong Xiang ◽

Kele Shen

Keyword(s):

Speed Test

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Test Infrastructure Development and Test Scheduling of 3D-Stacked ICs under Resource and Power Constraints

2015 IEEE 24th Asian Test Symposium (ATS) ◽

10.1109/ats.2015.20 ◽

2015 ◽

Author(s):

Rajit Karmakar ◽

Aditya Agarwal ◽

Santanu Chattopadhyay

Keyword(s):

Test Scheduling ◽

Infrastructure Development ◽

Power Constraints

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TestExpress - New Time-Effective Scan-Based Deterministic Test Paradigm

2015 IEEE 24th Asian Test Symposium (ATS) ◽

10.1109/ats.2015.11 ◽

2015 ◽

Cited By ~ 1

Author(s):

Grzegorz Mrugalski ◽

Janusz Rajski ◽

Jedrzej Solecki ◽

Jerzy Tyszer ◽

Chen Wang

Keyword(s):

New Time

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2015 IEEE 24th Asian Test Symposium (ATS) ◽

10.1109/ats.2015.4 ◽

2015 ◽

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SDC-TPG: A Deterministic Zero-Inflation Parallel Test Pattern Generator

2015 IEEE 24th Asian Test Symposium (ATS) ◽

10.1109/ats.2015.15 ◽

2015 ◽

Cited By ~ 1

Author(s):

Chun-Hao Chang ◽

Kuen-Wei Yeh ◽

Jiun-Lang Huang ◽

Laung-Terng Wang

Keyword(s):

Test Pattern ◽

Pattern Generator ◽

Zero Inflation ◽

Parallel Test

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Detection of test Patterns with Unreachable States through Efficient Inductive-Invariant Identification

2015 IEEE 24th Asian Test Symposium (ATS) ◽

10.1109/ats.2015.13 ◽

2015 ◽

Cited By ~ 3

Author(s):

Masahiro Fujita

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Securing IEEE 1687-2014 Standard Instrumentation Access by LFSR Key

2015 IEEE 24th Asian Test Symposium (ATS) ◽

10.1109/ats.2015.23 ◽

2015 ◽

Cited By ~ 11

Author(s):

Hejia Liu ◽

Vishwani D. Agrawal

Keyword(s):

Standard Instrumentation

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2015 IEEE 24th Asian Test Symposium (ATS)
Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Design-for-testability in reversible logic circuits based on bit-swapping

A Lightweight Timing Channel Protection for Shared Memory Controllers

Diagnostic Tests and Diagnosis for Delay Faults Using Path Segmentation

A Novel Scan Segmentation Design for Power Controllability and Reduction in At-Speed Test

Test Infrastructure Development and Test Scheduling of 3D-Stacked ICs under Resource and Power Constraints

TestExpress - New Time-Effective Scan-Based Deterministic Test Paradigm

Table of contents

SDC-TPG: A Deterministic Zero-Inflation Parallel Test Pattern Generator

Detection of test Patterns with Unreachable States through Efficient Inductive-Invariant Identification

Securing IEEE 1687-2014 Standard Instrumentation Access by LFSR Key

Export Citation Format

2015 IEEE 24th Asian Test Symposium (ATS)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Design-for-testability in reversible logic circuits based on bit-swapping

A Lightweight Timing Channel Protection for Shared Memory Controllers

Diagnostic Tests and Diagnosis for Delay Faults Using Path Segmentation

A Novel Scan Segmentation Design for Power Controllability and Reduction in At-Speed Test

Test Infrastructure Development and Test Scheduling of 3D-Stacked ICs under Resource and Power Constraints

TestExpress - New Time-Effective Scan-Based Deterministic Test Paradigm

Table of contents

SDC-TPG: A Deterministic Zero-Inflation Parallel Test Pattern Generator

Detection of test Patterns with Unreachable States through Efficient Inductive-Invariant Identification

Securing IEEE 1687-2014 Standard Instrumentation Access by LFSR Key

2015 IEEE 24th Asian Test Symposium (ATS)
Latest Publications